1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This is a target description file for the Intel i386 architecture, referred 11 // to here as the "X86" architecture. 12 // 13 //===----------------------------------------------------------------------===// 14 15 // Get the target-independent interfaces which we are implementing... 16 // 17 include "llvm/Target/Target.td" 18 19 //===----------------------------------------------------------------------===// 20 // X86 Subtarget state 21 // 22 23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", 24 "64-bit mode (x86_64)">; 25 26 //===----------------------------------------------------------------------===// 27 // X86 Subtarget features 28 //===----------------------------------------------------------------------===// 29 30 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", 31 "Enable conditional move instructions">; 32 33 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", 34 "Support POPCNT instruction">; 35 36 37 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", 38 "Enable MMX instructions">; 39 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", 40 "Enable SSE instructions", 41 // SSE codegen depends on cmovs, and all 42 // SSE1+ processors support them. 43 [FeatureMMX, FeatureCMOV]>; 44 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", 45 "Enable SSE2 instructions", 46 [FeatureSSE1]>; 47 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", 48 "Enable SSE3 instructions", 49 [FeatureSSE2]>; 50 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", 51 "Enable SSSE3 instructions", 52 [FeatureSSE3]>; 53 def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41", 54 "Enable SSE 4.1 instructions", 55 [FeatureSSSE3]>; 56 def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42", 57 "Enable SSE 4.2 instructions", 58 [FeatureSSE41]>; 59 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", 60 "Enable 3DNow! instructions", 61 [FeatureMMX]>; 62 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", 63 "Enable 3DNow! Athlon instructions", 64 [Feature3DNow]>; 65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied 66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels) 67 // without disabling 64-bit mode. 68 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", 69 "Support 64-bit instructions", 70 [FeatureCMOV]>; 71 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true", 72 "64-bit with cmpxchg16b", 73 [Feature64Bit]>; 74 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true", 75 "Bit testing of memory is slow">; 76 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem", 77 "IsUAMemFast", "true", 78 "Fast unaligned memory access">; 79 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", 80 "Support SSE 4a instructions", 81 [FeatureSSE3]>; 82 83 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX", 84 "Enable AVX instructions", 85 [FeatureSSE42]>; 86 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2", 87 "Enable AVX2 instructions", 88 [FeatureAVX]>; 89 def FeatureAVX512 : SubtargetFeature<"avx-512", "X86SSELevel", "AVX512", 90 "Enable AVX-512 instructions", 91 [FeatureAVX2]>; 92 def FeatureERI : SubtargetFeature<"avx-512-eri", "HasERI", "true", 93 "Enable AVX-512 Exponential and Reciprocal Instructions", 94 [FeatureAVX512]>; 95 def FeatureCDI : SubtargetFeature<"avx-512-cdi", "HasCDI", "true", 96 "Enable AVX-512 Conflict Detection Instructions", 97 [FeatureAVX512]>; 98 def FeaturePFI : SubtargetFeature<"avx-512-pfi", "HasPFI", "true", 99 "Enable AVX-512 PreFetch Instructions", 100 [FeatureAVX512]>; 101 102 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", 103 "Enable packed carry-less multiplication instructions", 104 [FeatureSSE2]>; 105 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", 106 "Enable three-operand fused multiple-add", 107 [FeatureAVX]>; 108 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", 109 "Enable four-operand fused multiple-add", 110 [FeatureAVX, FeatureSSE4A]>; 111 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", 112 "Enable XOP instructions", 113 [FeatureFMA4]>; 114 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", 115 "HasVectorUAMem", "true", 116 "Allow unaligned memory operands on vector/SIMD instructions">; 117 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 118 "Enable AES instructions", 119 [FeatureSSE2]>; 120 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", 121 "Support MOVBE instruction">; 122 def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true", 123 "Support RDRAND instruction">; 124 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", 125 "Support 16-bit floating point conversion instructions">; 126 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true", 127 "Support FS/GS Base instructions">; 128 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true", 129 "Support LZCNT instruction">; 130 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true", 131 "Support BMI instructions">; 132 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true", 133 "Support BMI2 instructions">; 134 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true", 135 "Support RTM instructions">; 136 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true", 137 "Support HLE">; 138 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true", 139 "Support ADX instructions">; 140 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", 141 "Support PRFCHW instructions">; 142 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", 143 "Support RDSEED instruction">; 144 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", 145 "Use LEA for adjusting the stack pointer">; 146 def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb", 147 "HasSlowDivide", "true", 148 "Use small divide for positive values less than 256">; 149 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", 150 "PadShortFunctions", "true", 151 "Pad short functions">; 152 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect", 153 "CallRegIndirect", "true", 154 "Call register indirect">; 155 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", 156 "LEA instruction needs inputs at AG stage">; 157 158 //===----------------------------------------------------------------------===// 159 // X86 processors supported. 160 //===----------------------------------------------------------------------===// 161 162 include "X86Schedule.td" 163 164 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom", 165 "Intel Atom processors">; 166 167 class Proc<string Name, list<SubtargetFeature> Features> 168 : ProcessorModel<Name, GenericModel, Features>; 169 170 def : Proc<"generic", []>; 171 def : Proc<"i386", []>; 172 def : Proc<"i486", []>; 173 def : Proc<"i586", []>; 174 def : Proc<"pentium", []>; 175 def : Proc<"pentium-mmx", [FeatureMMX]>; 176 def : Proc<"i686", []>; 177 def : Proc<"pentiumpro", [FeatureCMOV]>; 178 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>; 179 def : Proc<"pentium3", [FeatureSSE1]>; 180 def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>; 181 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>; 182 def : Proc<"pentium4", [FeatureSSE2]>; 183 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>; 184 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem, 185 FeatureFastUAMem]>; 186 // Intel Core Duo. 187 def : ProcessorModel<"yonah", SandyBridgeModel, 188 [FeatureSSE3, FeatureSlowBTMem]>; 189 190 // NetBurst. 191 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>; 192 def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>; 193 194 // Intel Core 2 Solo/Duo. 195 def : ProcessorModel<"core2", SandyBridgeModel, 196 [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>; 197 def : ProcessorModel<"penryn", SandyBridgeModel, 198 [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>; 199 200 // Atom. 201 def : ProcessorModel<"atom", AtomModel, 202 [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B, 203 FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP, 204 FeatureSlowDivide, 205 FeatureCallRegIndirect, 206 FeatureLEAUsesAG, 207 FeaturePadShortFunctions]>; 208 209 // "Arrandale" along with corei3 and corei5 210 def : ProcessorModel<"corei7", SandyBridgeModel, 211 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem, 212 FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>; 213 214 def : ProcessorModel<"nehalem", SandyBridgeModel, 215 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem, 216 FeatureFastUAMem, FeaturePOPCNT]>; 217 // Westmere is a similar machine to nehalem with some additional features. 218 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge 219 def : ProcessorModel<"westmere", SandyBridgeModel, 220 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem, 221 FeatureFastUAMem, FeaturePOPCNT, FeatureAES, 222 FeaturePCLMUL]>; 223 // Sandy Bridge 224 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE, 225 // rather than a superset. 226 def : ProcessorModel<"corei7-avx", SandyBridgeModel, 227 [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem, 228 FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>; 229 // Ivy Bridge 230 def : ProcessorModel<"core-avx-i", SandyBridgeModel, 231 [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem, 232 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND, 233 FeatureF16C, FeatureFSGSBase]>; 234 235 // Haswell 236 def : ProcessorModel<"core-avx2", HaswellModel, 237 [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem, 238 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND, 239 FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, 240 FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM, 241 FeatureHLE]>; 242 243 // KNL 244 // FIXME: define KNL model 245 def : ProcessorModel<"knl", HaswellModel, 246 [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI, 247 FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT, 248 FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C, 249 FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI, 250 FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE]>; 251 252 def : Proc<"k6", [FeatureMMX]>; 253 def : Proc<"k6-2", [Feature3DNow]>; 254 def : Proc<"k6-3", [Feature3DNow]>; 255 def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>; 256 def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>; 257 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 258 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 259 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 260 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit, 261 FeatureSlowBTMem]>; 262 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit, 263 FeatureSlowBTMem]>; 264 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit, 265 FeatureSlowBTMem]>; 266 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit, 267 FeatureSlowBTMem]>; 268 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B, 269 FeatureSlowBTMem]>; 270 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B, 271 FeatureSlowBTMem]>; 272 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B, 273 FeatureSlowBTMem]>; 274 def : Proc<"amdfam10", [FeatureSSE4A, 275 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT, 276 FeaturePOPCNT, FeatureSlowBTMem]>; 277 // Bobcat 278 def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B, 279 FeatureLZCNT, FeaturePOPCNT]>; 280 // Jaguar 281 def : Proc<"btver2", [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B, 282 FeatureAES, FeaturePCLMUL, FeatureBMI, 283 FeatureF16C, FeatureMOVBE, FeatureLZCNT, 284 FeaturePOPCNT]>; 285 // Bulldozer 286 def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, 287 FeatureAES, FeaturePCLMUL, 288 FeatureLZCNT, FeaturePOPCNT]>; 289 // Piledriver 290 def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, 291 FeatureAES, FeaturePCLMUL, 292 FeatureF16C, FeatureLZCNT, 293 FeaturePOPCNT, FeatureBMI, FeatureFMA]>; 294 def : Proc<"geode", [Feature3DNowA]>; 295 296 def : Proc<"winchip-c6", [FeatureMMX]>; 297 def : Proc<"winchip2", [Feature3DNow]>; 298 def : Proc<"c3", [Feature3DNow]>; 299 def : Proc<"c3-2", [FeatureSSE1]>; 300 301 //===----------------------------------------------------------------------===// 302 // Register File Description 303 //===----------------------------------------------------------------------===// 304 305 include "X86RegisterInfo.td" 306 307 //===----------------------------------------------------------------------===// 308 // Instruction Descriptions 309 //===----------------------------------------------------------------------===// 310 311 include "X86InstrInfo.td" 312 313 def X86InstrInfo : InstrInfo; 314 315 //===----------------------------------------------------------------------===// 316 // Calling Conventions 317 //===----------------------------------------------------------------------===// 318 319 include "X86CallingConv.td" 320 321 322 //===----------------------------------------------------------------------===// 323 // Assembly Parser 324 //===----------------------------------------------------------------------===// 325 326 def ATTAsmParser : AsmParser { 327 string AsmParserClassName = "AsmParser"; 328 } 329 330 def ATTAsmParserVariant : AsmParserVariant { 331 int Variant = 0; 332 333 // Variant name. 334 string Name = "att"; 335 336 // Discard comments in assembly strings. 337 string CommentDelimiter = "#"; 338 339 // Recognize hard coded registers. 340 string RegisterPrefix = "%"; 341 } 342 343 def IntelAsmParserVariant : AsmParserVariant { 344 int Variant = 1; 345 346 // Variant name. 347 string Name = "intel"; 348 349 // Discard comments in assembly strings. 350 string CommentDelimiter = ";"; 351 352 // Recognize hard coded registers. 353 string RegisterPrefix = ""; 354 } 355 356 //===----------------------------------------------------------------------===// 357 // Assembly Printers 358 //===----------------------------------------------------------------------===// 359 360 // The X86 target supports two different syntaxes for emitting machine code. 361 // This is controlled by the -x86-asm-syntax={att|intel} 362 def ATTAsmWriter : AsmWriter { 363 string AsmWriterClassName = "ATTInstPrinter"; 364 int Variant = 0; 365 bit isMCAsmWriter = 1; 366 } 367 def IntelAsmWriter : AsmWriter { 368 string AsmWriterClassName = "IntelInstPrinter"; 369 int Variant = 1; 370 bit isMCAsmWriter = 1; 371 } 372 373 def X86 : Target { 374 // Information about the instructions... 375 let InstructionSet = X86InstrInfo; 376 let AssemblyParsers = [ATTAsmParser]; 377 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant]; 378 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; 379 } 380
