1 //===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 jump, return, call, and related instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Control Flow Instructions. 16 // 17 18 // Return instructions. 19 // 20 // The X86retflag return instructions are variadic because we may add ST0 and 21 // ST1 arguments when returning values on the x87 stack. 22 let isTerminator = 1, isReturn = 1, isBarrier = 1, 23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in { 24 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops), 25 "ret", 26 [(X86retflag 0)], IIC_RET>; 27 def RETW : I <0xC3, RawFrm, (outs), (ins), 28 "ret{w}", 29 [], IIC_RET>, OpSize; 30 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 31 "ret\t$amt", 32 [(X86retflag timm:$amt)], IIC_RET_IMM>; 33 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), 34 "ret{w}\t$amt", 35 [], IIC_RET_IMM>, OpSize; 36 def LRETL : I <0xCB, RawFrm, (outs), (ins), 37 "{l}ret{l|f}", [], IIC_RET>; 38 def LRETW : I <0xCB, RawFrm, (outs), (ins), 39 "{l}ret{w|f}", [], IIC_RET>, OpSize; 40 def LRETQ : RI <0xCB, RawFrm, (outs), (ins), 41 "{l}ret{q|f}", [], IIC_RET>; 42 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 43 "{l}ret{l|f}\t$amt", [], IIC_RET>; 44 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 45 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize; 46 } 47 48 // Unconditional branches. 49 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { 50 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst), 51 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>; 52 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), 53 "jmp\t$dst", [], IIC_JMP_REL>; 54 // FIXME : Intel syntax for JMP64pcrel32 such that it is not ambiguious 55 // with JMP_1. 56 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst), 57 "jmpq\t$dst", [], IIC_JMP_REL>; 58 } 59 60 // Conditional Branches. 61 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in { 62 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> { 63 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [], 64 IIC_Jcc>; 65 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm, 66 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB; 67 } 68 } 69 70 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>; 71 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>; 72 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>; 73 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>; 74 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>; 75 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>; 76 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>; 77 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>; 78 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>; 79 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>; 80 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>; 81 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>; 82 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>; 83 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>; 84 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>; 85 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>; 86 87 // jcx/jecx/jrcx instructions. 88 let isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { 89 // These are the 32-bit versions of this instruction for the asmparser. In 90 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is 91 // jecxz. 92 let Uses = [CX] in 93 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 94 "jcxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In32BitMode]>; 95 let Uses = [ECX] in 96 def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 97 "jecxz\t$dst", [], IIC_JCXZ>, Requires<[In32BitMode]>; 98 99 // J*CXZ instruction: 64-bit versions of this instruction for the asmparser. 100 // In 64-bit mode, the address size prefix is jecxz and the unprefixed version 101 // is jrcxz. 102 let Uses = [ECX] in 103 def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 104 "jecxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In64BitMode]>; 105 let Uses = [RCX] in 106 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 107 "jrcxz\t$dst", [], IIC_JCXZ>, Requires<[In64BitMode]>; 108 } 109 110 // Indirect branches 111 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 112 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", 113 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[In32BitMode]>, 114 Sched<[WriteJump]>; 115 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", 116 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, 117 Requires<[In32BitMode]>, Sched<[WriteJumpLd]>; 118 119 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", 120 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>, 121 Sched<[WriteJump]>; 122 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", 123 [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>, 124 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>; 125 126 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), 127 (ins i16imm:$off, i16imm:$seg), 128 "ljmp{w}\t{$seg, $off|$off, $seg}", [], 129 IIC_JMP_FAR_PTR>, OpSize, Sched<[WriteJump]>; 130 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), 131 (ins i32imm:$off, i16imm:$seg), 132 "ljmp{l}\t{$seg, $off|$off, $seg}", [], 133 IIC_JMP_FAR_PTR>, Sched<[WriteJump]>; 134 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst), 135 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>, 136 Sched<[WriteJump]>; 137 138 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst), 139 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize, 140 Sched<[WriteJumpLd]>; 141 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst), 142 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, 143 Sched<[WriteJumpLd]>; 144 } 145 146 147 // Loop instructions 148 let SchedRW = [WriteJump] in { 149 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>; 150 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>; 151 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>; 152 } 153 154 //===----------------------------------------------------------------------===// 155 // Call Instructions... 156 // 157 let isCall = 1 in 158 // All calls clobber the non-callee saved registers. ESP is marked as 159 // a use to prevent stack-pointer assignments that appear immediately 160 // before calls from potentially appearing dead. Uses for argument 161 // registers are added manually. 162 let Uses = [ESP] in { 163 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm, 164 (outs), (ins i32imm_pcrel:$dst), 165 "call{l}\t$dst", [], IIC_CALL_RI>, 166 Requires<[In32BitMode]>, Sched<[WriteJump]>; 167 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst), 168 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>, 169 Requires<[In32BitMode]>, Sched<[WriteJump]>; 170 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst), 171 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], 172 IIC_CALL_MEM>, 173 Requires<[In32BitMode,FavorMemIndirectCall]>, 174 Sched<[WriteJumpLd]>; 175 176 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), 177 (ins i16imm:$off, i16imm:$seg), 178 "lcall{w}\t{$seg, $off|$off, $seg}", [], 179 IIC_CALL_FAR_PTR>, OpSize, Sched<[WriteJump]>; 180 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), 181 (ins i32imm:$off, i16imm:$seg), 182 "lcall{l}\t{$seg, $off|$off, $seg}", [], 183 IIC_CALL_FAR_PTR>, Sched<[WriteJump]>; 184 185 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst), 186 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize, 187 Sched<[WriteJumpLd]>; 188 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst), 189 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, 190 Sched<[WriteJumpLd]>; 191 192 // callw for 16 bit code for the assembler. 193 let isAsmParserOnly = 1 in 194 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm, 195 (outs), (ins i16imm_pcrel:$dst), 196 "callw\t$dst", []>, OpSize; 197 } 198 199 200 // Tail call stuff. 201 202 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 203 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in 204 let Uses = [ESP] in { 205 def TCRETURNdi : PseudoI<(outs), 206 (ins i32imm_pcrel:$dst, i32imm:$offset), []>; 207 def TCRETURNri : PseudoI<(outs), 208 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>; 209 let mayLoad = 1 in 210 def TCRETURNmi : PseudoI<(outs), 211 (ins i32mem_TC:$dst, i32imm:$offset), []>; 212 213 // FIXME: The should be pseudo instructions that are lowered when going to 214 // mcinst. 215 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs), 216 (ins i32imm_pcrel:$dst), 217 "jmp\t$dst # TAILCALL", 218 [], IIC_JMP_REL>; 219 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 220 "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead. 221 let mayLoad = 1 in 222 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst), 223 "jmp{l}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>; 224 } 225 226 227 //===----------------------------------------------------------------------===// 228 // Call Instructions... 229 // 230 231 // RSP is marked as a use to prevent stack-pointer assignments that appear 232 // immediately before calls from potentially appearing dead. Uses for argument 233 // registers are added manually. 234 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in { 235 // NOTE: this pattern doesn't match "X86call imm", because we do not know 236 // that the offset between an arbitrary immediate and the call will fit in 237 // the 32-bit pcrel field that we have. 238 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm, 239 (outs), (ins i64i32imm_pcrel:$dst), 240 "call{q}\t$dst", [], IIC_CALL_RI>, 241 Requires<[In64BitMode]>; 242 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst), 243 "call{q}\t{*}$dst", [(X86call GR64:$dst)], 244 IIC_CALL_RI>, 245 Requires<[In64BitMode]>; 246 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst), 247 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))], 248 IIC_CALL_MEM>, 249 Requires<[In64BitMode,FavorMemIndirectCall]>; 250 251 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst), 252 "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>; 253 } 254 255 let isCall = 1, isCodeGenOnly = 1 in 256 // __chkstk(MSVC): clobber R10, R11 and EFLAGS. 257 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP. 258 let Defs = [RAX, R10, R11, RSP, EFLAGS], 259 Uses = [RSP] in { 260 def W64ALLOCA : Ii32PCRel<0xE8, RawFrm, 261 (outs), (ins i64i32imm_pcrel:$dst), 262 "call{q}\t$dst", [], IIC_CALL_RI>, 263 Requires<[IsWin64]>, Sched<[WriteJump]>; 264 } 265 266 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 267 isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1, 268 SchedRW = [WriteJump] in { 269 def TCRETURNdi64 : PseudoI<(outs), 270 (ins i64i32imm_pcrel:$dst, i32imm:$offset), 271 []>; 272 def TCRETURNri64 : PseudoI<(outs), 273 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>; 274 let mayLoad = 1 in 275 def TCRETURNmi64 : PseudoI<(outs), 276 (ins i64mem_TC:$dst, i32imm:$offset), []>; 277 278 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), 279 (ins i64i32imm_pcrel:$dst), 280 "jmp\t$dst # TAILCALL", [], IIC_JMP_REL>; 281 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 282 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>; 283 284 let mayLoad = 1 in 285 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), 286 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>; 287 } 288
