1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // X86 Instruction Format Definitions. 12 // 13 14 // Format specifies the encoding used by the instruction. This is part of the 15 // ad-hoc solution used to emit machine instruction encodings by our machine 16 // code emitter. 17 class Format<bits<6> val> { 18 bits<6> Value = val; 19 } 20 21 def Pseudo : Format<0>; def RawFrm : Format<1>; 22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; 23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; 24 def MRMSrcMem : Format<6>; 25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; 26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; 27 def MRM6r : Format<22>; def MRM7r : Format<23>; 28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; 29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; 30 def MRM6m : Format<30>; def MRM7m : Format<31>; 31 def MRMInitReg : Format<32>; 32 def MRM_C1 : Format<33>; 33 def MRM_C2 : Format<34>; 34 def MRM_C3 : Format<35>; 35 def MRM_C4 : Format<36>; 36 def MRM_C8 : Format<37>; 37 def MRM_C9 : Format<38>; 38 def MRM_CA : Format<39>; 39 def MRM_CB : Format<40>; 40 def MRM_E8 : Format<41>; 41 def MRM_F0 : Format<42>; 42 def RawFrmImm8 : Format<43>; 43 def RawFrmImm16 : Format<44>; 44 def MRM_F8 : Format<45>; 45 def MRM_F9 : Format<46>; 46 def MRM_D0 : Format<47>; 47 def MRM_D1 : Format<48>; 48 def MRM_D4 : Format<49>; 49 def MRM_D5 : Format<50>; 50 def MRM_D6 : Format<51>; 51 def MRM_D8 : Format<52>; 52 def MRM_D9 : Format<53>; 53 def MRM_DA : Format<54>; 54 def MRM_DB : Format<55>; 55 def MRM_DC : Format<56>; 56 def MRM_DD : Format<57>; 57 def MRM_DE : Format<58>; 58 def MRM_DF : Format<59>; 59 60 // ImmType - This specifies the immediate type used by an instruction. This is 61 // part of the ad-hoc solution used to emit machine instruction encodings by our 62 // machine code emitter. 63 class ImmType<bits<3> val> { 64 bits<3> Value = val; 65 } 66 def NoImm : ImmType<0>; 67 def Imm8 : ImmType<1>; 68 def Imm8PCRel : ImmType<2>; 69 def Imm16 : ImmType<3>; 70 def Imm16PCRel : ImmType<4>; 71 def Imm32 : ImmType<5>; 72 def Imm32PCRel : ImmType<6>; 73 def Imm64 : ImmType<7>; 74 75 // FPFormat - This specifies what form this FP instruction has. This is used by 76 // the Floating-Point stackifier pass. 77 class FPFormat<bits<3> val> { 78 bits<3> Value = val; 79 } 80 def NotFP : FPFormat<0>; 81 def ZeroArgFP : FPFormat<1>; 82 def OneArgFP : FPFormat<2>; 83 def OneArgFPRW : FPFormat<3>; 84 def TwoArgFP : FPFormat<4>; 85 def CompareFP : FPFormat<5>; 86 def CondMovFP : FPFormat<6>; 87 def SpecialFP : FPFormat<7>; 88 89 // Class specifying the SSE execution domain, used by the SSEDomainFix pass. 90 // Keep in sync with tables in X86InstrInfo.cpp. 91 class Domain<bits<2> val> { 92 bits<2> Value = val; 93 } 94 def GenericDomain : Domain<0>; 95 def SSEPackedSingle : Domain<1>; 96 def SSEPackedDouble : Domain<2>; 97 def SSEPackedInt : Domain<3>; 98 99 // Class specifying the vector form of the decompressed 100 // displacement of 8-bit. 101 class CD8VForm<bits<3> val> { 102 bits<3> Value = val; 103 } 104 def CD8VF : CD8VForm<0>; // v := VL 105 def CD8VH : CD8VForm<1>; // v := VL/2 106 def CD8VQ : CD8VForm<2>; // v := VL/4 107 def CD8VO : CD8VForm<3>; // v := VL/8 108 def CD8VT1 : CD8VForm<4>; // v := 1 109 def CD8VT2 : CD8VForm<5>; // v := 2 110 def CD8VT4 : CD8VForm<6>; // v := 4 111 def CD8VT8 : CD8VForm<7>; // v := 8 112 113 // Prefix byte classes which are used to indicate to the ad-hoc machine code 114 // emitter that various prefix bytes are required. 115 class OpSize { bit hasOpSizePrefix = 1; } 116 class AdSize { bit hasAdSizePrefix = 1; } 117 class REX_W { bit hasREX_WPrefix = 1; } 118 class LOCK { bit hasLockPrefix = 1; } 119 class SegFS { bits<2> SegOvrBits = 1; } 120 class SegGS { bits<2> SegOvrBits = 2; } 121 class TB { bits<5> Prefix = 1; } 122 class REP { bits<5> Prefix = 2; } 123 class D8 { bits<5> Prefix = 3; } 124 class D9 { bits<5> Prefix = 4; } 125 class DA { bits<5> Prefix = 5; } 126 class DB { bits<5> Prefix = 6; } 127 class DC { bits<5> Prefix = 7; } 128 class DD { bits<5> Prefix = 8; } 129 class DE { bits<5> Prefix = 9; } 130 class DF { bits<5> Prefix = 10; } 131 class XD { bits<5> Prefix = 11; } 132 class XS { bits<5> Prefix = 12; } 133 class T8 { bits<5> Prefix = 13; } 134 class TA { bits<5> Prefix = 14; } 135 class A6 { bits<5> Prefix = 15; } 136 class A7 { bits<5> Prefix = 16; } 137 class T8XD { bits<5> Prefix = 17; } 138 class T8XS { bits<5> Prefix = 18; } 139 class TAXD { bits<5> Prefix = 19; } 140 class XOP8 { bits<5> Prefix = 20; } 141 class XOP9 { bits<5> Prefix = 21; } 142 class VEX { bit hasVEXPrefix = 1; } 143 class VEX_W { bit hasVEX_WPrefix = 1; } 144 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; } 145 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; } 146 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; } 147 class VEX_L { bit hasVEX_L = 1; } 148 class VEX_LIG { bit ignoresVEX_L = 1; } 149 class EVEX : VEX { bit hasEVEXPrefix = 1; } 150 class EVEX_4V : VEX_4V { bit hasEVEXPrefix = 1; } 151 class EVEX_K { bit hasEVEX_K = 1; } 152 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; } 153 class EVEX_B { bit hasEVEX_B = 1; } 154 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; } 155 class EVEX_CD8<int esize, CD8VForm form> { 156 bits<2> EVEX_CD8E = !if(!eq(esize, 8), 0b00, 157 !if(!eq(esize, 16), 0b01, 158 !if(!eq(esize, 32), 0b10, 159 !if(!eq(esize, 64), 0b11, ?)))); 160 bits<3> EVEX_CD8V = form.Value; 161 } 162 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; } 163 class MemOp4 { bit hasMemOp4Prefix = 1; } 164 class XOP { bit hasXOP_Prefix = 1; } 165 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins, 166 string AsmStr, 167 InstrItinClass itin, 168 Domain d = GenericDomain> 169 : Instruction { 170 let Namespace = "X86"; 171 172 bits<8> Opcode = opcod; 173 Format Form = f; 174 bits<6> FormBits = Form.Value; 175 ImmType ImmT = i; 176 177 dag OutOperandList = outs; 178 dag InOperandList = ins; 179 string AsmString = AsmStr; 180 181 // If this is a pseudo instruction, mark it isCodeGenOnly. 182 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 183 184 let Itinerary = itin; 185 186 // 187 // Attributes specific to X86 instructions... 188 // 189 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? 190 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix? 191 192 bits<5> Prefix = 0; // Which prefix byte does this inst have? 193 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix? 194 FPFormat FPForm = NotFP; // What flavor of FP instruction is this? 195 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? 196 bits<2> SegOvrBits = 0; // Segment override prefix. 197 Domain ExeDomain = d; 198 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix? 199 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field? 200 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field? 201 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to 202 // encode the third operand? 203 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register 204 // to be encoded in a immediate field? 205 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers? 206 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit 207 bit hasEVEXPrefix = 0; // Does this inst require EVEX form? 208 bit hasEVEX_K = 0; // Does this inst require masking? 209 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field? 210 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field? 211 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field? 212 bits<2> EVEX_CD8E = 0; // Compressed disp8 form - element-size. 213 bits<3> EVEX_CD8V = 0; // Compressed disp8 form - vector-width. 214 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding? 215 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands 216 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix? 217 218 // TSFlags layout should be kept in sync with X86InstrInfo.h. 219 let TSFlags{5-0} = FormBits; 220 let TSFlags{6} = hasOpSizePrefix; 221 let TSFlags{7} = hasAdSizePrefix; 222 let TSFlags{12-8} = Prefix; 223 let TSFlags{13} = hasREX_WPrefix; 224 let TSFlags{16-14} = ImmT.Value; 225 let TSFlags{19-17} = FPForm.Value; 226 let TSFlags{20} = hasLockPrefix; 227 let TSFlags{22-21} = SegOvrBits; 228 let TSFlags{24-23} = ExeDomain.Value; 229 let TSFlags{32-25} = Opcode; 230 let TSFlags{33} = hasVEXPrefix; 231 let TSFlags{34} = hasVEX_WPrefix; 232 let TSFlags{35} = hasVEX_4VPrefix; 233 let TSFlags{36} = hasVEX_4VOp3Prefix; 234 let TSFlags{37} = hasVEX_i8ImmReg; 235 let TSFlags{38} = hasVEX_L; 236 let TSFlags{39} = ignoresVEX_L; 237 let TSFlags{40} = hasEVEXPrefix; 238 let TSFlags{41} = hasEVEX_K; 239 let TSFlags{42} = hasEVEX_Z; 240 let TSFlags{43} = hasEVEX_L2; 241 let TSFlags{44} = hasEVEX_B; 242 let TSFlags{46-45} = EVEX_CD8E; 243 let TSFlags{49-47} = EVEX_CD8V; 244 let TSFlags{50} = has3DNow0F0FOpcode; 245 let TSFlags{51} = hasMemOp4Prefix; 246 let TSFlags{52} = hasXOP_Prefix; 247 } 248 249 class PseudoI<dag oops, dag iops, list<dag> pattern> 250 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> { 251 let Pattern = pattern; 252 } 253 254 class I<bits<8> o, Format f, dag outs, dag ins, string asm, 255 list<dag> pattern, InstrItinClass itin = NoItinerary, 256 Domain d = GenericDomain> 257 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> { 258 let Pattern = pattern; 259 let CodeSize = 3; 260 } 261 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm, 262 list<dag> pattern, InstrItinClass itin = NoItinerary, 263 Domain d = GenericDomain> 264 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> { 265 let Pattern = pattern; 266 let CodeSize = 3; 267 } 268 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 269 list<dag> pattern, InstrItinClass itin = NoItinerary> 270 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> { 271 let Pattern = pattern; 272 let CodeSize = 3; 273 } 274 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm, 275 list<dag> pattern, InstrItinClass itin = NoItinerary> 276 : X86Inst<o, f, Imm16, outs, ins, asm, itin> { 277 let Pattern = pattern; 278 let CodeSize = 3; 279 } 280 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm, 281 list<dag> pattern, InstrItinClass itin = NoItinerary> 282 : X86Inst<o, f, Imm32, outs, ins, asm, itin> { 283 let Pattern = pattern; 284 let CodeSize = 3; 285 } 286 287 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 288 list<dag> pattern, InstrItinClass itin = NoItinerary> 289 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> { 290 let Pattern = pattern; 291 let CodeSize = 3; 292 } 293 294 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 295 list<dag> pattern, InstrItinClass itin = NoItinerary> 296 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> { 297 let Pattern = pattern; 298 let CodeSize = 3; 299 } 300 301 // FPStack Instruction Templates: 302 // FPI - Floating Point Instruction template. 303 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm, 304 InstrItinClass itin = NoItinerary> 305 : I<o, F, outs, ins, asm, [], itin> {} 306 307 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated. 308 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern, 309 InstrItinClass itin = NoItinerary> 310 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> { 311 let FPForm = fp; 312 let Pattern = pattern; 313 } 314 315 // Templates for instructions that use a 16- or 32-bit segmented address as 316 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP) 317 // 318 // Iseg16 - 16-bit segment selector, 16-bit offset 319 // Iseg32 - 16-bit segment selector, 32-bit offset 320 321 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm, 322 list<dag> pattern, InstrItinClass itin = NoItinerary> 323 : X86Inst<o, f, Imm16, outs, ins, asm, itin> { 324 let Pattern = pattern; 325 let CodeSize = 3; 326 } 327 328 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm, 329 list<dag> pattern, InstrItinClass itin = NoItinerary> 330 : X86Inst<o, f, Imm32, outs, ins, asm, itin> { 331 let Pattern = pattern; 332 let CodeSize = 3; 333 } 334 335 def __xs : XS; 336 def __xd : XD; 337 338 // SI - SSE 1 & 2 scalar instructions 339 class SI<bits<8> o, Format F, dag outs, dag ins, string asm, 340 list<dag> pattern, InstrItinClass itin = NoItinerary> 341 : I<o, F, outs, ins, asm, pattern, itin> { 342 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX], 343 !if(!eq(Prefix, __xs.Prefix), [UseSSE1], 344 !if(!eq(Prefix, __xd.Prefix), [UseSSE2], 345 !if(hasOpSizePrefix, [UseSSE2], [UseSSE1])))); 346 347 // AVX instructions have a 'v' prefix in the mnemonic 348 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm); 349 } 350 351 // SIi8 - SSE 1 & 2 scalar instructions 352 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 353 list<dag> pattern, InstrItinClass itin = NoItinerary> 354 : Ii8<o, F, outs, ins, asm, pattern, itin> { 355 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX], 356 !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2])); 357 358 // AVX instructions have a 'v' prefix in the mnemonic 359 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm); 360 } 361 362 // PI - SSE 1 & 2 packed instructions 363 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, 364 InstrItinClass itin, Domain d> 365 : I<o, F, outs, ins, asm, pattern, itin, d> { 366 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX], 367 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])); 368 369 // AVX instructions have a 'v' prefix in the mnemonic 370 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm); 371 } 372 373 // MMXPI - SSE 1 & 2 packed instructions with MMX operands 374 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, 375 InstrItinClass itin, Domain d> 376 : I<o, F, outs, ins, asm, pattern, itin, d> { 377 let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]); 378 } 379 380 // PIi8 - SSE 1 & 2 packed instructions with immediate 381 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 382 list<dag> pattern, InstrItinClass itin, Domain d> 383 : Ii8<o, F, outs, ins, asm, pattern, itin, d> { 384 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX], 385 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])); 386 387 // AVX instructions have a 'v' prefix in the mnemonic 388 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm); 389 } 390 391 // SSE1 Instruction Templates: 392 // 393 // SSI - SSE1 instructions with XS prefix. 394 // PSI - SSE1 instructions with TB prefix. 395 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix. 396 // VSSI - SSE1 instructions with XS prefix in AVX form. 397 // VPSI - SSE1 instructions with TB prefix in AVX form, packed single. 398 399 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, 400 list<dag> pattern, InstrItinClass itin = NoItinerary> 401 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>; 402 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 403 list<dag> pattern, InstrItinClass itin = NoItinerary> 404 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>; 405 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, 406 list<dag> pattern, InstrItinClass itin = NoItinerary> 407 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB, 408 Requires<[UseSSE1]>; 409 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 410 list<dag> pattern, InstrItinClass itin = NoItinerary> 411 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB, 412 Requires<[UseSSE1]>; 413 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm, 414 list<dag> pattern, InstrItinClass itin = NoItinerary> 415 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS, 416 Requires<[HasAVX]>; 417 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm, 418 list<dag> pattern, InstrItinClass itin = NoItinerary> 419 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB, 420 Requires<[HasAVX]>; 421 422 // SSE2 Instruction Templates: 423 // 424 // SDI - SSE2 instructions with XD prefix. 425 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. 426 // S2SI - SSE2 instructions with XS prefix. 427 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. 428 // PDI - SSE2 instructions with TB and OpSize prefixes, packed double domain. 429 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes. 430 // VSDI - SSE2 scalar instructions with XD prefix in AVX form. 431 // VPDI - SSE2 vector instructions with TB and OpSize prefixes in AVX form, 432 // packed double domain. 433 // VS2I - SSE2 scalar instructions with TB and OpSize prefixes in AVX form. 434 // S2I - SSE2 scalar instructions with TB and OpSize prefixes. 435 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as 436 // MMX operands. 437 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as 438 // MMX operands. 439 440 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, 441 list<dag> pattern, InstrItinClass itin = NoItinerary> 442 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>; 443 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 444 list<dag> pattern, InstrItinClass itin = NoItinerary> 445 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>; 446 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm, 447 list<dag> pattern, InstrItinClass itin = NoItinerary> 448 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>; 449 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 450 list<dag> pattern, InstrItinClass itin = NoItinerary> 451 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>; 452 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, 453 list<dag> pattern, InstrItinClass itin = NoItinerary> 454 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize, 455 Requires<[UseSSE2]>; 456 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 457 list<dag> pattern, InstrItinClass itin = NoItinerary> 458 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize, 459 Requires<[UseSSE2]>; 460 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm, 461 list<dag> pattern, InstrItinClass itin = NoItinerary> 462 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD, 463 Requires<[HasAVX]>; 464 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm, 465 list<dag> pattern, InstrItinClass itin = NoItinerary> 466 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS, 467 Requires<[HasAVX]>; 468 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm, 469 list<dag> pattern, InstrItinClass itin = NoItinerary> 470 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB, 471 OpSize, Requires<[HasAVX]>; 472 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 473 list<dag> pattern, InstrItinClass itin = NoItinerary> 474 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, TB, 475 OpSize, Requires<[HasAVX]>; 476 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm, 477 list<dag> pattern, InstrItinClass itin = NoItinerary> 478 : I<o, F, outs, ins, asm, pattern, itin>, TB, 479 OpSize, Requires<[UseSSE2]>; 480 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 481 list<dag> pattern, InstrItinClass itin = NoItinerary> 482 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>; 483 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 484 list<dag> pattern, InstrItinClass itin = NoItinerary> 485 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>; 486 487 // SSE3 Instruction Templates: 488 // 489 // S3I - SSE3 instructions with TB and OpSize prefixes. 490 // S3SI - SSE3 instructions with XS prefix. 491 // S3DI - SSE3 instructions with XD prefix. 492 493 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, 494 list<dag> pattern, InstrItinClass itin = NoItinerary> 495 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS, 496 Requires<[UseSSE3]>; 497 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, 498 list<dag> pattern, InstrItinClass itin = NoItinerary> 499 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD, 500 Requires<[UseSSE3]>; 501 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, 502 list<dag> pattern, InstrItinClass itin = NoItinerary> 503 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize, 504 Requires<[UseSSE3]>; 505 506 507 // SSSE3 Instruction Templates: 508 // 509 // SS38I - SSSE3 instructions with T8 prefix. 510 // SS3AI - SSSE3 instructions with TA prefix. 511 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands. 512 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands. 513 // 514 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version 515 // uses the MMX registers. The 64-bit versions are grouped with the MMX 516 // classes. They need to be enabled even if AVX is enabled. 517 518 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm, 519 list<dag> pattern, InstrItinClass itin = NoItinerary> 520 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, 521 Requires<[UseSSSE3]>; 522 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, 523 list<dag> pattern, InstrItinClass itin = NoItinerary> 524 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, 525 Requires<[UseSSSE3]>; 526 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm, 527 list<dag> pattern, InstrItinClass itin = NoItinerary> 528 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, 529 Requires<[HasSSSE3]>; 530 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, 531 list<dag> pattern, InstrItinClass itin = NoItinerary> 532 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, 533 Requires<[HasSSSE3]>; 534 535 // SSE4.1 Instruction Templates: 536 // 537 // SS48I - SSE 4.1 instructions with T8 prefix. 538 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8. 539 // 540 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm, 541 list<dag> pattern, InstrItinClass itin = NoItinerary> 542 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, 543 Requires<[UseSSE41]>; 544 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 545 list<dag> pattern, InstrItinClass itin = NoItinerary> 546 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, 547 Requires<[UseSSE41]>; 548 549 // SSE4.2 Instruction Templates: 550 // 551 // SS428I - SSE 4.2 instructions with T8 prefix. 552 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm, 553 list<dag> pattern, InstrItinClass itin = NoItinerary> 554 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, 555 Requires<[UseSSE42]>; 556 557 // SS42FI - SSE 4.2 instructions with T8XD prefix. 558 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns. 559 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm, 560 list<dag> pattern, InstrItinClass itin = NoItinerary> 561 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>; 562 563 // SS42AI = SSE 4.2 instructions with TA prefix 564 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm, 565 list<dag> pattern, InstrItinClass itin = NoItinerary> 566 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, 567 Requires<[UseSSE42]>; 568 569 // AVX Instruction Templates: 570 // Instructions introduced in AVX (no SSE equivalent forms) 571 // 572 // AVX8I - AVX instructions with T8 and OpSize prefix. 573 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8. 574 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm, 575 list<dag> pattern, InstrItinClass itin = NoItinerary> 576 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize, 577 Requires<[HasAVX]>; 578 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 579 list<dag> pattern, InstrItinClass itin = NoItinerary> 580 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize, 581 Requires<[HasAVX]>; 582 583 // AVX2 Instruction Templates: 584 // Instructions introduced in AVX2 (no SSE equivalent forms) 585 // 586 // AVX28I - AVX2 instructions with T8 and OpSize prefix. 587 // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8. 588 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm, 589 list<dag> pattern, InstrItinClass itin = NoItinerary> 590 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize, 591 Requires<[HasAVX2]>; 592 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 593 list<dag> pattern, InstrItinClass itin = NoItinerary> 594 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize, 595 Requires<[HasAVX2]>; 596 597 598 // AVX-512 Instruction Templates: 599 // Instructions introduced in AVX-512 (no SSE equivalent forms) 600 // 601 // AVX5128I - AVX-512 instructions with T8 and OpSize prefix. 602 // AVX512AIi8 - AVX-512 instructions with TA, OpSize prefix and ImmT = Imm8. 603 // AVX512PDI - AVX-512 instructions with TB, OpSize, double packed. 604 // AVX512PSI - AVX-512 instructions with TB, single packed. 605 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes. 606 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain. 607 // AVX512BI - AVX-512 instructions with TB, OpSize, int packed domain. 608 // AVX512SI - AVX-512 scalar instructions with TB and OpSize prefixes. 609 610 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm, 611 list<dag> pattern, InstrItinClass itin = NoItinerary> 612 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize, 613 Requires<[HasAVX512]>; 614 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm, 615 list<dag> pattern, InstrItinClass itin = NoItinerary> 616 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS, 617 Requires<[HasAVX512]>; 618 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm, 619 list<dag> pattern, InstrItinClass itin = NoItinerary> 620 : I<o, F, outs, ins, asm, pattern, itin>, XS, 621 Requires<[HasAVX512]>; 622 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm, 623 list<dag> pattern, InstrItinClass itin = NoItinerary> 624 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD, 625 Requires<[HasAVX512]>; 626 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm, 627 list<dag> pattern, InstrItinClass itin = NoItinerary> 628 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize, 629 Requires<[HasAVX512]>; 630 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 631 list<dag> pattern, InstrItinClass itin = NoItinerary> 632 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize, 633 Requires<[HasAVX512]>; 634 class AVX512SI<bits<8> o, Format F, dag outs, dag ins, string asm, 635 list<dag> pattern, InstrItinClass itin = NoItinerary> 636 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize, 637 Requires<[HasAVX512]>; 638 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 639 list<dag> pattern, InstrItinClass itin = NoItinerary> 640 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize, 641 Requires<[HasAVX512]>; 642 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm, 643 list<dag> pattern, InstrItinClass itin = NoItinerary> 644 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, 645 Requires<[HasAVX512]>; 646 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm, 647 list<dag> pattern, InstrItinClass itin = NoItinerary> 648 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, 649 OpSize, Requires<[HasAVX512]>; 650 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm, 651 list<dag> pattern, InstrItinClass itin = NoItinerary> 652 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB, 653 Requires<[HasAVX512]>; 654 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 655 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary> 656 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>; 657 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm, 658 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary> 659 : I<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>; 660 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm, 661 list<dag>pattern, InstrItinClass itin = NoItinerary> 662 : I<o, F, outs, ins, asm, pattern, itin>, T8, 663 OpSize, EVEX_4V, Requires<[HasAVX512]>; 664 665 // AES Instruction Templates: 666 // 667 // AES8I 668 // These use the same encoding as the SSE4.2 T8 and TA encodings. 669 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm, 670 list<dag>pattern, InstrItinClass itin = NoItinerary> 671 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, 672 Requires<[HasAES]>; 673 674 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm, 675 list<dag> pattern, InstrItinClass itin = NoItinerary> 676 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, 677 Requires<[HasAES]>; 678 679 // PCLMUL Instruction Templates 680 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 681 list<dag>pattern, InstrItinClass itin = NoItinerary> 682 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, 683 OpSize, Requires<[HasPCLMUL]>; 684 685 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 686 list<dag>pattern, InstrItinClass itin = NoItinerary> 687 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, 688 OpSize, VEX_4V, Requires<[HasAVX, HasPCLMUL]>; 689 690 // FMA3 Instruction Templates 691 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm, 692 list<dag>pattern, InstrItinClass itin = NoItinerary> 693 : I<o, F, outs, ins, asm, pattern, itin>, T8, 694 OpSize, VEX_4V, FMASC, Requires<[HasFMA]>; 695 696 // FMA4 Instruction Templates 697 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm, 698 list<dag>pattern, InstrItinClass itin = NoItinerary> 699 : Ii8<o, F, outs, ins, asm, pattern, itin>, TA, 700 OpSize, VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>; 701 702 // XOP 2, 3 and 4 Operand Instruction Template 703 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm, 704 list<dag> pattern, InstrItinClass itin = NoItinerary> 705 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, 706 XOP, XOP9, Requires<[HasXOP]>; 707 708 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte 709 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm, 710 list<dag> pattern, InstrItinClass itin = NoItinerary> 711 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, 712 XOP, XOP8, Requires<[HasXOP]>; 713 714 // XOP 5 operand instruction (VEX encoding!) 715 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm, 716 list<dag>pattern, InstrItinClass itin = NoItinerary> 717 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, 718 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>; 719 720 // X86-64 Instruction templates... 721 // 722 723 class RI<bits<8> o, Format F, dag outs, dag ins, string asm, 724 list<dag> pattern, InstrItinClass itin = NoItinerary> 725 : I<o, F, outs, ins, asm, pattern, itin>, REX_W; 726 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm, 727 list<dag> pattern, InstrItinClass itin = NoItinerary> 728 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W; 729 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm, 730 list<dag> pattern, InstrItinClass itin = NoItinerary> 731 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W; 732 733 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm, 734 list<dag> pattern, InstrItinClass itin = NoItinerary> 735 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W { 736 let Pattern = pattern; 737 let CodeSize = 3; 738 } 739 740 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm, 741 list<dag> pattern, InstrItinClass itin = NoItinerary> 742 : X86Inst<o, f, Imm64, outs, ins, asm, itin> { 743 let Pattern = pattern; 744 let CodeSize = 3; 745 } 746 747 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm, 748 list<dag> pattern, InstrItinClass itin = NoItinerary> 749 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W; 750 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm, 751 list<dag> pattern, InstrItinClass itin = NoItinerary> 752 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W; 753 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm, 754 list<dag> pattern, InstrItinClass itin = NoItinerary> 755 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W; 756 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm, 757 list<dag> pattern, InstrItinClass itin = NoItinerary> 758 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W; 759 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 760 list<dag> pattern, InstrItinClass itin = NoItinerary> 761 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W; 762 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 763 list<dag> pattern, InstrItinClass itin = NoItinerary> 764 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W; 765 766 // MMX Instruction templates 767 // 768 769 // MMXI - MMX instructions with TB prefix. 770 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode. 771 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes. 772 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. 773 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. 774 // MMXID - MMX instructions with XD prefix. 775 // MMXIS - MMX instructions with XS prefix. 776 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, 777 list<dag> pattern, InstrItinClass itin = NoItinerary> 778 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>; 779 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm, 780 list<dag> pattern, InstrItinClass itin = NoItinerary> 781 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>; 782 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, 783 list<dag> pattern, InstrItinClass itin = NoItinerary> 784 : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>; 785 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, 786 list<dag> pattern, InstrItinClass itin = NoItinerary> 787 : I<o, F, outs, ins, asm, pattern, itin>, TB, OpSize, Requires<[HasMMX]>; 788 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 789 list<dag> pattern, InstrItinClass itin = NoItinerary> 790 : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>; 791 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, 792 list<dag> pattern, InstrItinClass itin = NoItinerary> 793 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>; 794 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, 795 list<dag> pattern, InstrItinClass itin = NoItinerary> 796 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>; 797
