1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the machine model for Sandy Bridge to support instruction 11 // scheduling and other instruction cost heuristics. 12 // 13 //===----------------------------------------------------------------------===// 14 15 def SandyBridgeModel : SchedMachineModel { 16 // All x86 instructions are modeled as a single micro-op, and SB can decode 4 17 // instructions per cycle. 18 // FIXME: Identify instructions that aren't a single fused micro-op. 19 let IssueWidth = 4; 20 let MicroOpBufferSize = 168; // Based on the reorder buffer. 21 let LoadLatency = 4; 22 let MispredictPenalty = 16; 23 } 24 25 let SchedModel = SandyBridgeModel in { 26 27 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle. 28 29 // Ports 0, 1, and 5 handle all computation. 30 def SBPort0 : ProcResource<1>; 31 def SBPort1 : ProcResource<1>; 32 def SBPort5 : ProcResource<1>; 33 34 // Ports 2 and 3 are identical. They handle loads and the address half of 35 // stores. 36 def SBPort23 : ProcResource<2>; 37 38 // Port 4 gets the data half of stores. Store data can be available later than 39 // the store address, but since we don't model the latency of stores, we can 40 // ignore that. 41 def SBPort4 : ProcResource<1>; 42 43 // Many micro-ops are capable of issuing on multiple ports. 44 def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; 45 def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; 46 def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; 47 48 // 54 Entry Unified Scheduler 49 def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> { 50 let BufferSize=54; 51 } 52 53 // Integer division issued on port 0. 54 def SBDivider : ProcResource<1>; 55 56 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4 57 // cycles after the memory operand. 58 def : ReadAdvance<ReadAfterLd, 4>; 59 60 // Many SchedWrites are defined in pairs with and without a folded load. 61 // Instructions with folded loads are usually micro-fused, so they only appear 62 // as two micro-ops when queued in the reservation station. 63 // This multiclass defines the resource usage for variants with and without 64 // folded loads. 65 multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW, 66 ProcResourceKind ExePort, 67 int Lat> { 68 // Register variant is using a single cycle on ExePort. 69 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; } 70 71 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the 72 // latency. 73 def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> { 74 let Latency = !add(Lat, 4); 75 } 76 } 77 78 // A folded store needs a cycle on port 4 for the store data, but it does not 79 // need an extra port 2/3 cycle to recompute the address. 80 def : WriteRes<WriteRMW, [SBPort4]>; 81 82 def : WriteRes<WriteStore, [SBPort23, SBPort4]>; 83 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 4; } 84 def : WriteRes<WriteMove, [SBPort015]>; 85 def : WriteRes<WriteZero, []>; 86 87 defm : SBWriteResPair<WriteALU, SBPort015, 1>; 88 defm : SBWriteResPair<WriteIMul, SBPort1, 3>; 89 def : WriteRes<WriteIMulH, []> { let Latency = 3; } 90 defm : SBWriteResPair<WriteShift, SBPort05, 1>; 91 defm : SBWriteResPair<WriteJump, SBPort5, 1>; 92 93 // This is for simple LEAs with one or two input operands. 94 // The complex ones can only execute on port 1, and they require two cycles on 95 // the port to read all inputs. We don't model that. 96 def : WriteRes<WriteLEA, [SBPort15]>; 97 98 // This is quite rough, latency depends on the dividend. 99 def : WriteRes<WriteIDiv, [SBPort0, SBDivider]> { 100 let Latency = 25; 101 let ResourceCycles = [1, 10]; 102 } 103 def : WriteRes<WriteIDivLd, [SBPort23, SBPort0, SBDivider]> { 104 let Latency = 29; 105 let ResourceCycles = [1, 1, 10]; 106 } 107 108 // Scalar and vector floating point. 109 defm : SBWriteResPair<WriteFAdd, SBPort1, 3>; 110 defm : SBWriteResPair<WriteFMul, SBPort0, 5>; 111 defm : SBWriteResPair<WriteFDiv, SBPort0, 12>; // 10-14 cycles. 112 defm : SBWriteResPair<WriteFRcp, SBPort0, 5>; 113 defm : SBWriteResPair<WriteFSqrt, SBPort0, 15>; 114 defm : SBWriteResPair<WriteCvtF2I, SBPort1, 3>; 115 defm : SBWriteResPair<WriteCvtI2F, SBPort1, 4>; 116 defm : SBWriteResPair<WriteCvtF2F, SBPort1, 3>; 117 118 // Vector integer operations. 119 defm : SBWriteResPair<WriteVecShift, SBPort05, 1>; 120 defm : SBWriteResPair<WriteVecLogic, SBPort015, 1>; 121 defm : SBWriteResPair<WriteVecALU, SBPort15, 1>; 122 defm : SBWriteResPair<WriteVecIMul, SBPort0, 5>; 123 defm : SBWriteResPair<WriteShuffle, SBPort15, 1>; 124 125 def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; } 126 def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; } 127 } // SchedModel 128
