1 //===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 // InstrSchedModel annotations for out-of-order CPUs. 11 // 12 // These annotations are independent of the itinerary classes defined below. 13 14 // Instructions with folded loads need to read the memory operand immediately, 15 // but other register operands don't have to be read until the load is ready. 16 // These operands are marked with ReadAfterLd. 17 def ReadAfterLd : SchedRead; 18 19 // Instructions with both a load and a store folded are modeled as a folded 20 // load + WriteRMW. 21 def WriteRMW : SchedWrite; 22 23 // Most instructions can fold loads, so almost every SchedWrite comes in two 24 // variants: With and without a folded load. 25 // An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite 26 // with a folded load. 27 class X86FoldableSchedWrite : SchedWrite { 28 // The SchedWrite to use when a load is folded into the instruction. 29 SchedWrite Folded; 30 } 31 32 // Multiclass that produces a linked pair of SchedWrites. 33 multiclass X86SchedWritePair { 34 // Register-Memory operation. 35 def Ld : SchedWrite; 36 // Register-Register operation. 37 def NAME : X86FoldableSchedWrite { 38 let Folded = !cast<SchedWrite>(NAME#"Ld"); 39 } 40 } 41 42 // Arithmetic. 43 defm WriteALU : X86SchedWritePair; // Simple integer ALU op. 44 defm WriteIMul : X86SchedWritePair; // Integer multiplication. 45 def WriteIMulH : SchedWrite; // Integer multiplication, high part. 46 defm WriteIDiv : X86SchedWritePair; // Integer division. 47 def WriteLEA : SchedWrite; // LEA instructions can't fold loads. 48 49 // Integer shifts and rotates. 50 defm WriteShift : X86SchedWritePair; 51 52 // Loads, stores, and moves, not folded with other operations. 53 def WriteLoad : SchedWrite; 54 def WriteStore : SchedWrite; 55 def WriteMove : SchedWrite; 56 57 // Idioms that clear a register, like xorps %xmm0, %xmm0. 58 // These can often bypass execution ports completely. 59 def WriteZero : SchedWrite; 60 61 // Branches don't produce values, so they have no latency, but they still 62 // consume resources. Indirect branches can fold loads. 63 defm WriteJump : X86SchedWritePair; 64 65 // Floating point. This covers both scalar and vector operations. 66 defm WriteFAdd : X86SchedWritePair; // Floating point add/sub/compare. 67 defm WriteFMul : X86SchedWritePair; // Floating point multiplication. 68 defm WriteFDiv : X86SchedWritePair; // Floating point division. 69 defm WriteFSqrt : X86SchedWritePair; // Floating point square root. 70 defm WriteFRcp : X86SchedWritePair; // Floating point reciprocal. 71 defm WriteFMA : X86SchedWritePair; // Fused Multiply Add. 72 73 // FMA Scheduling helper class. 74 class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 75 76 // Vector integer operations. 77 defm WriteVecALU : X86SchedWritePair; // Vector integer ALU op, no logicals. 78 defm WriteVecShift : X86SchedWritePair; // Vector integer shifts. 79 defm WriteVecIMul : X86SchedWritePair; // Vector integer multiply. 80 81 // Vector bitwise operations. 82 // These are often used on both floating point and integer vectors. 83 defm WriteVecLogic : X86SchedWritePair; // Vector and/or/xor. 84 defm WriteShuffle : X86SchedWritePair; // Vector shuffles and blends. 85 86 // Conversion between integer and float. 87 defm WriteCvtF2I : X86SchedWritePair; // Float -> Integer. 88 defm WriteCvtI2F : X86SchedWritePair; // Integer -> Float. 89 defm WriteCvtF2F : X86SchedWritePair; // Float -> Float size conversion. 90 91 // Catch-all for expensive system instructions. 92 def WriteSystem : SchedWrite; 93 94 // Old microcoded instructions that nobody use. 95 def WriteMicrocoded : SchedWrite; 96 97 //===----------------------------------------------------------------------===// 98 // Instruction Itinerary classes used for X86 99 def IIC_ALU_MEM : InstrItinClass; 100 def IIC_ALU_NONMEM : InstrItinClass; 101 def IIC_LEA : InstrItinClass; 102 def IIC_LEA_16 : InstrItinClass; 103 def IIC_MUL8 : InstrItinClass; 104 def IIC_MUL16_MEM : InstrItinClass; 105 def IIC_MUL16_REG : InstrItinClass; 106 def IIC_MUL32_MEM : InstrItinClass; 107 def IIC_MUL32_REG : InstrItinClass; 108 def IIC_MUL64 : InstrItinClass; 109 // imul by al, ax, eax, tax 110 def IIC_IMUL8 : InstrItinClass; 111 def IIC_IMUL16_MEM : InstrItinClass; 112 def IIC_IMUL16_REG : InstrItinClass; 113 def IIC_IMUL32_MEM : InstrItinClass; 114 def IIC_IMUL32_REG : InstrItinClass; 115 def IIC_IMUL64 : InstrItinClass; 116 // imul reg by reg|mem 117 def IIC_IMUL16_RM : InstrItinClass; 118 def IIC_IMUL16_RR : InstrItinClass; 119 def IIC_IMUL32_RM : InstrItinClass; 120 def IIC_IMUL32_RR : InstrItinClass; 121 def IIC_IMUL64_RM : InstrItinClass; 122 def IIC_IMUL64_RR : InstrItinClass; 123 // imul reg = reg/mem * imm 124 def IIC_IMUL16_RMI : InstrItinClass; 125 def IIC_IMUL16_RRI : InstrItinClass; 126 def IIC_IMUL32_RMI : InstrItinClass; 127 def IIC_IMUL32_RRI : InstrItinClass; 128 def IIC_IMUL64_RMI : InstrItinClass; 129 def IIC_IMUL64_RRI : InstrItinClass; 130 // div 131 def IIC_DIV8_MEM : InstrItinClass; 132 def IIC_DIV8_REG : InstrItinClass; 133 def IIC_DIV16 : InstrItinClass; 134 def IIC_DIV32 : InstrItinClass; 135 def IIC_DIV64 : InstrItinClass; 136 // idiv 137 def IIC_IDIV8 : InstrItinClass; 138 def IIC_IDIV16 : InstrItinClass; 139 def IIC_IDIV32 : InstrItinClass; 140 def IIC_IDIV64 : InstrItinClass; 141 // neg/not/inc/dec 142 def IIC_UNARY_REG : InstrItinClass; 143 def IIC_UNARY_MEM : InstrItinClass; 144 // add/sub/and/or/xor/adc/sbc/cmp/test 145 def IIC_BIN_MEM : InstrItinClass; 146 def IIC_BIN_NONMEM : InstrItinClass; 147 // shift/rotate 148 def IIC_SR : InstrItinClass; 149 // shift double 150 def IIC_SHD16_REG_IM : InstrItinClass; 151 def IIC_SHD16_REG_CL : InstrItinClass; 152 def IIC_SHD16_MEM_IM : InstrItinClass; 153 def IIC_SHD16_MEM_CL : InstrItinClass; 154 def IIC_SHD32_REG_IM : InstrItinClass; 155 def IIC_SHD32_REG_CL : InstrItinClass; 156 def IIC_SHD32_MEM_IM : InstrItinClass; 157 def IIC_SHD32_MEM_CL : InstrItinClass; 158 def IIC_SHD64_REG_IM : InstrItinClass; 159 def IIC_SHD64_REG_CL : InstrItinClass; 160 def IIC_SHD64_MEM_IM : InstrItinClass; 161 def IIC_SHD64_MEM_CL : InstrItinClass; 162 // cmov 163 def IIC_CMOV16_RM : InstrItinClass; 164 def IIC_CMOV16_RR : InstrItinClass; 165 def IIC_CMOV32_RM : InstrItinClass; 166 def IIC_CMOV32_RR : InstrItinClass; 167 def IIC_CMOV64_RM : InstrItinClass; 168 def IIC_CMOV64_RR : InstrItinClass; 169 // set 170 def IIC_SET_R : InstrItinClass; 171 def IIC_SET_M : InstrItinClass; 172 // jmp/jcc/jcxz 173 def IIC_Jcc : InstrItinClass; 174 def IIC_JCXZ : InstrItinClass; 175 def IIC_JMP_REL : InstrItinClass; 176 def IIC_JMP_REG : InstrItinClass; 177 def IIC_JMP_MEM : InstrItinClass; 178 def IIC_JMP_FAR_MEM : InstrItinClass; 179 def IIC_JMP_FAR_PTR : InstrItinClass; 180 // loop 181 def IIC_LOOP : InstrItinClass; 182 def IIC_LOOPE : InstrItinClass; 183 def IIC_LOOPNE : InstrItinClass; 184 // call 185 def IIC_CALL_RI : InstrItinClass; 186 def IIC_CALL_MEM : InstrItinClass; 187 def IIC_CALL_FAR_MEM : InstrItinClass; 188 def IIC_CALL_FAR_PTR : InstrItinClass; 189 // ret 190 def IIC_RET : InstrItinClass; 191 def IIC_RET_IMM : InstrItinClass; 192 //sign extension movs 193 def IIC_MOVSX : InstrItinClass; 194 def IIC_MOVSX_R16_R8 : InstrItinClass; 195 def IIC_MOVSX_R16_M8 : InstrItinClass; 196 def IIC_MOVSX_R16_R16 : InstrItinClass; 197 def IIC_MOVSX_R32_R32 : InstrItinClass; 198 //zero extension movs 199 def IIC_MOVZX : InstrItinClass; 200 def IIC_MOVZX_R16_R8 : InstrItinClass; 201 def IIC_MOVZX_R16_M8 : InstrItinClass; 202 203 def IIC_REP_MOVS : InstrItinClass; 204 def IIC_REP_STOS : InstrItinClass; 205 206 // SSE scalar/parallel binary operations 207 def IIC_SSE_ALU_F32S_RR : InstrItinClass; 208 def IIC_SSE_ALU_F32S_RM : InstrItinClass; 209 def IIC_SSE_ALU_F64S_RR : InstrItinClass; 210 def IIC_SSE_ALU_F64S_RM : InstrItinClass; 211 def IIC_SSE_MUL_F32S_RR : InstrItinClass; 212 def IIC_SSE_MUL_F32S_RM : InstrItinClass; 213 def IIC_SSE_MUL_F64S_RR : InstrItinClass; 214 def IIC_SSE_MUL_F64S_RM : InstrItinClass; 215 def IIC_SSE_DIV_F32S_RR : InstrItinClass; 216 def IIC_SSE_DIV_F32S_RM : InstrItinClass; 217 def IIC_SSE_DIV_F64S_RR : InstrItinClass; 218 def IIC_SSE_DIV_F64S_RM : InstrItinClass; 219 def IIC_SSE_ALU_F32P_RR : InstrItinClass; 220 def IIC_SSE_ALU_F32P_RM : InstrItinClass; 221 def IIC_SSE_ALU_F64P_RR : InstrItinClass; 222 def IIC_SSE_ALU_F64P_RM : InstrItinClass; 223 def IIC_SSE_MUL_F32P_RR : InstrItinClass; 224 def IIC_SSE_MUL_F32P_RM : InstrItinClass; 225 def IIC_SSE_MUL_F64P_RR : InstrItinClass; 226 def IIC_SSE_MUL_F64P_RM : InstrItinClass; 227 def IIC_SSE_DIV_F32P_RR : InstrItinClass; 228 def IIC_SSE_DIV_F32P_RM : InstrItinClass; 229 def IIC_SSE_DIV_F64P_RR : InstrItinClass; 230 def IIC_SSE_DIV_F64P_RM : InstrItinClass; 231 232 def IIC_SSE_COMIS_RR : InstrItinClass; 233 def IIC_SSE_COMIS_RM : InstrItinClass; 234 235 def IIC_SSE_HADDSUB_RR : InstrItinClass; 236 def IIC_SSE_HADDSUB_RM : InstrItinClass; 237 238 def IIC_SSE_BIT_P_RR : InstrItinClass; 239 def IIC_SSE_BIT_P_RM : InstrItinClass; 240 241 def IIC_SSE_INTALU_P_RR : InstrItinClass; 242 def IIC_SSE_INTALU_P_RM : InstrItinClass; 243 def IIC_SSE_INTALUQ_P_RR : InstrItinClass; 244 def IIC_SSE_INTALUQ_P_RM : InstrItinClass; 245 246 def IIC_SSE_INTMUL_P_RR : InstrItinClass; 247 def IIC_SSE_INTMUL_P_RM : InstrItinClass; 248 249 def IIC_SSE_INTSH_P_RR : InstrItinClass; 250 def IIC_SSE_INTSH_P_RM : InstrItinClass; 251 def IIC_SSE_INTSH_P_RI : InstrItinClass; 252 253 def IIC_SSE_CMPP_RR : InstrItinClass; 254 def IIC_SSE_CMPP_RM : InstrItinClass; 255 256 def IIC_SSE_SHUFP : InstrItinClass; 257 def IIC_SSE_PSHUF : InstrItinClass; 258 259 def IIC_SSE_UNPCK : InstrItinClass; 260 261 def IIC_SSE_MOVMSK : InstrItinClass; 262 def IIC_SSE_MASKMOV : InstrItinClass; 263 264 def IIC_SSE_PEXTRW : InstrItinClass; 265 def IIC_SSE_PINSRW : InstrItinClass; 266 267 def IIC_SSE_PABS_RR : InstrItinClass; 268 def IIC_SSE_PABS_RM : InstrItinClass; 269 270 def IIC_SSE_SQRTPS_RR : InstrItinClass; 271 def IIC_SSE_SQRTPS_RM : InstrItinClass; 272 def IIC_SSE_SQRTSS_RR : InstrItinClass; 273 def IIC_SSE_SQRTSS_RM : InstrItinClass; 274 def IIC_SSE_SQRTPD_RR : InstrItinClass; 275 def IIC_SSE_SQRTPD_RM : InstrItinClass; 276 def IIC_SSE_SQRTSD_RR : InstrItinClass; 277 def IIC_SSE_SQRTSD_RM : InstrItinClass; 278 279 def IIC_SSE_RCPP_RR : InstrItinClass; 280 def IIC_SSE_RCPP_RM : InstrItinClass; 281 def IIC_SSE_RCPS_RR : InstrItinClass; 282 def IIC_SSE_RCPS_RM : InstrItinClass; 283 284 def IIC_SSE_MOV_S_RR : InstrItinClass; 285 def IIC_SSE_MOV_S_RM : InstrItinClass; 286 def IIC_SSE_MOV_S_MR : InstrItinClass; 287 288 def IIC_SSE_MOVA_P_RR : InstrItinClass; 289 def IIC_SSE_MOVA_P_RM : InstrItinClass; 290 def IIC_SSE_MOVA_P_MR : InstrItinClass; 291 292 def IIC_SSE_MOVU_P_RR : InstrItinClass; 293 def IIC_SSE_MOVU_P_RM : InstrItinClass; 294 def IIC_SSE_MOVU_P_MR : InstrItinClass; 295 296 def IIC_SSE_MOVDQ : InstrItinClass; 297 def IIC_SSE_MOVD_ToGP : InstrItinClass; 298 def IIC_SSE_MOVQ_RR : InstrItinClass; 299 300 def IIC_SSE_MOV_LH : InstrItinClass; 301 302 def IIC_SSE_LDDQU : InstrItinClass; 303 304 def IIC_SSE_MOVNT : InstrItinClass; 305 306 def IIC_SSE_PHADDSUBD_RR : InstrItinClass; 307 def IIC_SSE_PHADDSUBD_RM : InstrItinClass; 308 def IIC_SSE_PHADDSUBSW_RR : InstrItinClass; 309 def IIC_SSE_PHADDSUBSW_RM : InstrItinClass; 310 def IIC_SSE_PHADDSUBW_RR : InstrItinClass; 311 def IIC_SSE_PHADDSUBW_RM : InstrItinClass; 312 def IIC_SSE_PSHUFB_RR : InstrItinClass; 313 def IIC_SSE_PSHUFB_RM : InstrItinClass; 314 def IIC_SSE_PSIGN_RR : InstrItinClass; 315 def IIC_SSE_PSIGN_RM : InstrItinClass; 316 317 def IIC_SSE_PMADD : InstrItinClass; 318 def IIC_SSE_PMULHRSW : InstrItinClass; 319 def IIC_SSE_PALIGNR : InstrItinClass; 320 def IIC_SSE_MWAIT : InstrItinClass; 321 def IIC_SSE_MONITOR : InstrItinClass; 322 323 def IIC_SSE_PREFETCH : InstrItinClass; 324 def IIC_SSE_PAUSE : InstrItinClass; 325 def IIC_SSE_LFENCE : InstrItinClass; 326 def IIC_SSE_MFENCE : InstrItinClass; 327 def IIC_SSE_SFENCE : InstrItinClass; 328 def IIC_SSE_LDMXCSR : InstrItinClass; 329 def IIC_SSE_STMXCSR : InstrItinClass; 330 331 def IIC_SSE_CVT_PD_RR : InstrItinClass; 332 def IIC_SSE_CVT_PD_RM : InstrItinClass; 333 def IIC_SSE_CVT_PS_RR : InstrItinClass; 334 def IIC_SSE_CVT_PS_RM : InstrItinClass; 335 def IIC_SSE_CVT_PI2PS_RR : InstrItinClass; 336 def IIC_SSE_CVT_PI2PS_RM : InstrItinClass; 337 def IIC_SSE_CVT_Scalar_RR : InstrItinClass; 338 def IIC_SSE_CVT_Scalar_RM : InstrItinClass; 339 def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass; 340 def IIC_SSE_CVT_SS2SI32_RR : InstrItinClass; 341 def IIC_SSE_CVT_SS2SI64_RM : InstrItinClass; 342 def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass; 343 def IIC_SSE_CVT_SD2SI_RM : InstrItinClass; 344 def IIC_SSE_CVT_SD2SI_RR : InstrItinClass; 345 346 // MMX 347 def IIC_MMX_MOV_MM_RM : InstrItinClass; 348 def IIC_MMX_MOV_REG_MM : InstrItinClass; 349 def IIC_MMX_MOVQ_RM : InstrItinClass; 350 def IIC_MMX_MOVQ_RR : InstrItinClass; 351 352 def IIC_MMX_ALU_RM : InstrItinClass; 353 def IIC_MMX_ALU_RR : InstrItinClass; 354 def IIC_MMX_ALUQ_RM : InstrItinClass; 355 def IIC_MMX_ALUQ_RR : InstrItinClass; 356 def IIC_MMX_PHADDSUBW_RM : InstrItinClass; 357 def IIC_MMX_PHADDSUBW_RR : InstrItinClass; 358 def IIC_MMX_PHADDSUBD_RM : InstrItinClass; 359 def IIC_MMX_PHADDSUBD_RR : InstrItinClass; 360 def IIC_MMX_PMUL : InstrItinClass; 361 def IIC_MMX_MISC_FUNC_MEM : InstrItinClass; 362 def IIC_MMX_MISC_FUNC_REG : InstrItinClass; 363 def IIC_MMX_PSADBW : InstrItinClass; 364 def IIC_MMX_SHIFT_RI : InstrItinClass; 365 def IIC_MMX_SHIFT_RM : InstrItinClass; 366 def IIC_MMX_SHIFT_RR : InstrItinClass; 367 def IIC_MMX_UNPCK_H_RM : InstrItinClass; 368 def IIC_MMX_UNPCK_H_RR : InstrItinClass; 369 def IIC_MMX_UNPCK_L : InstrItinClass; 370 def IIC_MMX_PCK_RM : InstrItinClass; 371 def IIC_MMX_PCK_RR : InstrItinClass; 372 def IIC_MMX_PSHUF : InstrItinClass; 373 def IIC_MMX_PEXTR : InstrItinClass; 374 def IIC_MMX_PINSRW : InstrItinClass; 375 def IIC_MMX_MASKMOV : InstrItinClass; 376 377 def IIC_MMX_CVT_PD_RR : InstrItinClass; 378 def IIC_MMX_CVT_PD_RM : InstrItinClass; 379 def IIC_MMX_CVT_PS_RR : InstrItinClass; 380 def IIC_MMX_CVT_PS_RM : InstrItinClass; 381 382 def IIC_CMPX_LOCK : InstrItinClass; 383 def IIC_CMPX_LOCK_8 : InstrItinClass; 384 def IIC_CMPX_LOCK_8B : InstrItinClass; 385 def IIC_CMPX_LOCK_16B : InstrItinClass; 386 387 def IIC_XADD_LOCK_MEM : InstrItinClass; 388 def IIC_XADD_LOCK_MEM8 : InstrItinClass; 389 390 def IIC_FILD : InstrItinClass; 391 def IIC_FLD : InstrItinClass; 392 def IIC_FLD80 : InstrItinClass; 393 def IIC_FST : InstrItinClass; 394 def IIC_FST80 : InstrItinClass; 395 def IIC_FIST : InstrItinClass; 396 def IIC_FLDZ : InstrItinClass; 397 def IIC_FUCOM : InstrItinClass; 398 def IIC_FUCOMI : InstrItinClass; 399 def IIC_FCOMI : InstrItinClass; 400 def IIC_FNSTSW : InstrItinClass; 401 def IIC_FNSTCW : InstrItinClass; 402 def IIC_FLDCW : InstrItinClass; 403 def IIC_FNINIT : InstrItinClass; 404 def IIC_FFREE : InstrItinClass; 405 def IIC_FNCLEX : InstrItinClass; 406 def IIC_WAIT : InstrItinClass; 407 def IIC_FXAM : InstrItinClass; 408 def IIC_FNOP : InstrItinClass; 409 def IIC_FLDL : InstrItinClass; 410 def IIC_F2XM1 : InstrItinClass; 411 def IIC_FYL2X : InstrItinClass; 412 def IIC_FPTAN : InstrItinClass; 413 def IIC_FPATAN : InstrItinClass; 414 def IIC_FXTRACT : InstrItinClass; 415 def IIC_FPREM1 : InstrItinClass; 416 def IIC_FPSTP : InstrItinClass; 417 def IIC_FPREM : InstrItinClass; 418 def IIC_FYL2XP1 : InstrItinClass; 419 def IIC_FSINCOS : InstrItinClass; 420 def IIC_FRNDINT : InstrItinClass; 421 def IIC_FSCALE : InstrItinClass; 422 def IIC_FCOMPP : InstrItinClass; 423 def IIC_FXSAVE : InstrItinClass; 424 def IIC_FXRSTOR : InstrItinClass; 425 426 def IIC_FXCH : InstrItinClass; 427 428 // System instructions 429 def IIC_CPUID : InstrItinClass; 430 def IIC_INT : InstrItinClass; 431 def IIC_INT3 : InstrItinClass; 432 def IIC_INVD : InstrItinClass; 433 def IIC_INVLPG : InstrItinClass; 434 def IIC_IRET : InstrItinClass; 435 def IIC_HLT : InstrItinClass; 436 def IIC_LXS : InstrItinClass; 437 def IIC_LTR : InstrItinClass; 438 def IIC_RDTSC : InstrItinClass; 439 def IIC_RSM : InstrItinClass; 440 def IIC_SIDT : InstrItinClass; 441 def IIC_SGDT : InstrItinClass; 442 def IIC_SLDT : InstrItinClass; 443 def IIC_STR : InstrItinClass; 444 def IIC_SWAPGS : InstrItinClass; 445 def IIC_SYSCALL : InstrItinClass; 446 def IIC_SYS_ENTER_EXIT : InstrItinClass; 447 def IIC_IN_RR : InstrItinClass; 448 def IIC_IN_RI : InstrItinClass; 449 def IIC_OUT_RR : InstrItinClass; 450 def IIC_OUT_IR : InstrItinClass; 451 def IIC_INS : InstrItinClass; 452 def IIC_MOV_REG_DR : InstrItinClass; 453 def IIC_MOV_DR_REG : InstrItinClass; 454 def IIC_MOV_REG_CR : InstrItinClass; 455 def IIC_MOV_CR_REG : InstrItinClass; 456 def IIC_MOV_REG_SR : InstrItinClass; 457 def IIC_MOV_MEM_SR : InstrItinClass; 458 def IIC_MOV_SR_REG : InstrItinClass; 459 def IIC_MOV_SR_MEM : InstrItinClass; 460 def IIC_LAR_RM : InstrItinClass; 461 def IIC_LAR_RR : InstrItinClass; 462 def IIC_LSL_RM : InstrItinClass; 463 def IIC_LSL_RR : InstrItinClass; 464 def IIC_LGDT : InstrItinClass; 465 def IIC_LIDT : InstrItinClass; 466 def IIC_LLDT_REG : InstrItinClass; 467 def IIC_LLDT_MEM : InstrItinClass; 468 def IIC_PUSH_CS : InstrItinClass; 469 def IIC_PUSH_SR : InstrItinClass; 470 def IIC_POP_SR : InstrItinClass; 471 def IIC_POP_SR_SS : InstrItinClass; 472 def IIC_VERR : InstrItinClass; 473 def IIC_VERW_REG : InstrItinClass; 474 def IIC_VERW_MEM : InstrItinClass; 475 def IIC_WRMSR : InstrItinClass; 476 def IIC_RDMSR : InstrItinClass; 477 def IIC_RDPMC : InstrItinClass; 478 def IIC_SMSW : InstrItinClass; 479 def IIC_LMSW_REG : InstrItinClass; 480 def IIC_LMSW_MEM : InstrItinClass; 481 def IIC_ENTER : InstrItinClass; 482 def IIC_LEAVE : InstrItinClass; 483 def IIC_POP_MEM : InstrItinClass; 484 def IIC_POP_REG16 : InstrItinClass; 485 def IIC_POP_REG : InstrItinClass; 486 def IIC_POP_F : InstrItinClass; 487 def IIC_POP_FD : InstrItinClass; 488 def IIC_POP_A : InstrItinClass; 489 def IIC_PUSH_IMM : InstrItinClass; 490 def IIC_PUSH_MEM : InstrItinClass; 491 def IIC_PUSH_REG : InstrItinClass; 492 def IIC_PUSH_F : InstrItinClass; 493 def IIC_PUSH_A : InstrItinClass; 494 def IIC_BSWAP : InstrItinClass; 495 def IIC_BSF : InstrItinClass; 496 def IIC_BSR : InstrItinClass; 497 def IIC_MOVS : InstrItinClass; 498 def IIC_STOS : InstrItinClass; 499 def IIC_SCAS : InstrItinClass; 500 def IIC_CMPS : InstrItinClass; 501 def IIC_MOV : InstrItinClass; 502 def IIC_MOV_MEM : InstrItinClass; 503 def IIC_AHF : InstrItinClass; 504 def IIC_BT_MI : InstrItinClass; 505 def IIC_BT_MR : InstrItinClass; 506 def IIC_BT_RI : InstrItinClass; 507 def IIC_BT_RR : InstrItinClass; 508 def IIC_BTX_MI : InstrItinClass; 509 def IIC_BTX_MR : InstrItinClass; 510 def IIC_BTX_RI : InstrItinClass; 511 def IIC_BTX_RR : InstrItinClass; 512 def IIC_XCHG_REG : InstrItinClass; 513 def IIC_XCHG_MEM : InstrItinClass; 514 def IIC_XADD_REG : InstrItinClass; 515 def IIC_XADD_MEM : InstrItinClass; 516 def IIC_CMPXCHG_MEM : InstrItinClass; 517 def IIC_CMPXCHG_REG : InstrItinClass; 518 def IIC_CMPXCHG_MEM8 : InstrItinClass; 519 def IIC_CMPXCHG_REG8 : InstrItinClass; 520 def IIC_CMPXCHG_8B : InstrItinClass; 521 def IIC_CMPXCHG_16B : InstrItinClass; 522 def IIC_LODS : InstrItinClass; 523 def IIC_OUTS : InstrItinClass; 524 def IIC_CLC : InstrItinClass; 525 def IIC_CLD : InstrItinClass; 526 def IIC_CLI : InstrItinClass; 527 def IIC_CMC : InstrItinClass; 528 def IIC_CLTS : InstrItinClass; 529 def IIC_STC : InstrItinClass; 530 def IIC_STI : InstrItinClass; 531 def IIC_STD : InstrItinClass; 532 def IIC_XLAT : InstrItinClass; 533 def IIC_AAA : InstrItinClass; 534 def IIC_AAD : InstrItinClass; 535 def IIC_AAM : InstrItinClass; 536 def IIC_AAS : InstrItinClass; 537 def IIC_DAA : InstrItinClass; 538 def IIC_DAS : InstrItinClass; 539 def IIC_BOUND : InstrItinClass; 540 def IIC_ARPL_REG : InstrItinClass; 541 def IIC_ARPL_MEM : InstrItinClass; 542 def IIC_MOVBE : InstrItinClass; 543 544 def IIC_NOP : InstrItinClass; 545 546 //===----------------------------------------------------------------------===// 547 // Processor instruction itineraries. 548 549 // IssueWidth is analagous to the number of decode units. Core and its 550 // descendents, including Nehalem and SandyBridge have 4 decoders. 551 // Resources beyond the decoder operate on micro-ops and are bufferred 552 // so adjacent micro-ops don't directly compete. 553 // 554 // MicroOpBufferSize > 1 indicates that RAW dependencies can be 555 // decoded in the same cycle. The value 32 is a reasonably arbitrary 556 // number of in-flight instructions. 557 // 558 // HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef 559 // indicates high latency opcodes. Alternatively, InstrItinData 560 // entries may be included here to define specific operand 561 // latencies. Since these latencies are not used for pipeline hazards, 562 // they do not need to be exact. 563 // 564 // The GenericModel contains no instruciton itineraries. 565 def GenericModel : SchedMachineModel { 566 let IssueWidth = 4; 567 let MicroOpBufferSize = 32; 568 let LoadLatency = 4; 569 let HighLatency = 10; 570 } 571 572 include "X86ScheduleAtom.td" 573 include "X86SchedSandyBridge.td" 574 include "X86SchedHaswell.td" 575
