1 //===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the XCore implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef XCOREINSTRUCTIONINFO_H 15 #define XCOREINSTRUCTIONINFO_H 16 17 #include "XCoreRegisterInfo.h" 18 #include "llvm/Target/TargetInstrInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #include "XCoreGenInstrInfo.inc" 22 23 namespace llvm { 24 25 class XCoreInstrInfo : public XCoreGenInstrInfo { 26 const XCoreRegisterInfo RI; 27 public: 28 XCoreInstrInfo(); 29 30 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 31 /// such, whenever a client has an instance of instruction info, it should 32 /// always be able to get register info as well (through this method). 33 /// 34 virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } 35 36 /// isLoadFromStackSlot - If the specified machine instruction is a direct 37 /// load from a stack slot, return the virtual or physical register number of 38 /// the destination along with the FrameIndex of the loaded stack slot. If 39 /// not, return 0. This predicate must return 0 if the instruction has 40 /// any side effects other than loading from the stack slot. 41 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 42 int &FrameIndex) const; 43 44 /// isStoreToStackSlot - If the specified machine instruction is a direct 45 /// store to a stack slot, return the virtual or physical register number of 46 /// the source reg along with the FrameIndex of the loaded stack slot. If 47 /// not, return 0. This predicate must return 0 if the instruction has 48 /// any side effects other than storing to the stack slot. 49 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 50 int &FrameIndex) const; 51 52 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 53 MachineBasicBlock *&FBB, 54 SmallVectorImpl<MachineOperand> &Cond, 55 bool AllowModify) const; 56 57 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 58 MachineBasicBlock *FBB, 59 const SmallVectorImpl<MachineOperand> &Cond, 60 DebugLoc DL) const; 61 62 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 63 64 virtual void copyPhysReg(MachineBasicBlock &MBB, 65 MachineBasicBlock::iterator I, DebugLoc DL, 66 unsigned DestReg, unsigned SrcReg, 67 bool KillSrc) const; 68 69 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 70 MachineBasicBlock::iterator MI, 71 unsigned SrcReg, bool isKill, int FrameIndex, 72 const TargetRegisterClass *RC, 73 const TargetRegisterInfo *TRI) const; 74 75 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 76 MachineBasicBlock::iterator MI, 77 unsigned DestReg, int FrameIndex, 78 const TargetRegisterClass *RC, 79 const TargetRegisterInfo *TRI) const; 80 81 virtual bool ReverseBranchCondition( 82 SmallVectorImpl<MachineOperand> &Cond) const; 83 }; 84 85 } 86 87 #endif 88
