1 ; Test 32-bit compare and swap. 2 ; 3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 4 5 ; Check the low end of the CS range. 6 define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) { 7 ; CHECK-LABEL: f1: 8 ; CHECK: cs %r2, %r3, 0(%r4) 9 ; CHECK: br %r14 10 %val = cmpxchg i32 *%src, i32 %cmp, i32 %swap seq_cst 11 ret i32 %val 12 } 13 14 ; Check the high end of the aligned CS range. 15 define i32 @f2(i32 %cmp, i32 %swap, i32 *%src) { 16 ; CHECK-LABEL: f2: 17 ; CHECK: cs %r2, %r3, 4092(%r4) 18 ; CHECK: br %r14 19 %ptr = getelementptr i32 *%src, i64 1023 20 %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst 21 ret i32 %val 22 } 23 24 ; Check the next word up, which should use CSY instead of CS. 25 define i32 @f3(i32 %cmp, i32 %swap, i32 *%src) { 26 ; CHECK-LABEL: f3: 27 ; CHECK: csy %r2, %r3, 4096(%r4) 28 ; CHECK: br %r14 29 %ptr = getelementptr i32 *%src, i64 1024 30 %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst 31 ret i32 %val 32 } 33 34 ; Check the high end of the aligned CSY range. 35 define i32 @f4(i32 %cmp, i32 %swap, i32 *%src) { 36 ; CHECK-LABEL: f4: 37 ; CHECK: csy %r2, %r3, 524284(%r4) 38 ; CHECK: br %r14 39 %ptr = getelementptr i32 *%src, i64 131071 40 %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst 41 ret i32 %val 42 } 43 44 ; Check the next word up, which needs separate address logic. 45 ; Other sequences besides this one would be OK. 46 define i32 @f5(i32 %cmp, i32 %swap, i32 *%src) { 47 ; CHECK-LABEL: f5: 48 ; CHECK: agfi %r4, 524288 49 ; CHECK: cs %r2, %r3, 0(%r4) 50 ; CHECK: br %r14 51 %ptr = getelementptr i32 *%src, i64 131072 52 %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst 53 ret i32 %val 54 } 55 56 ; Check the high end of the negative aligned CSY range. 57 define i32 @f6(i32 %cmp, i32 %swap, i32 *%src) { 58 ; CHECK-LABEL: f6: 59 ; CHECK: csy %r2, %r3, -4(%r4) 60 ; CHECK: br %r14 61 %ptr = getelementptr i32 *%src, i64 -1 62 %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst 63 ret i32 %val 64 } 65 66 ; Check the low end of the CSY range. 67 define i32 @f7(i32 %cmp, i32 %swap, i32 *%src) { 68 ; CHECK-LABEL: f7: 69 ; CHECK: csy %r2, %r3, -524288(%r4) 70 ; CHECK: br %r14 71 %ptr = getelementptr i32 *%src, i64 -131072 72 %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst 73 ret i32 %val 74 } 75 76 ; Check the next word down, which needs separate address logic. 77 ; Other sequences besides this one would be OK. 78 define i32 @f8(i32 %cmp, i32 %swap, i32 *%src) { 79 ; CHECK-LABEL: f8: 80 ; CHECK: agfi %r4, -524292 81 ; CHECK: cs %r2, %r3, 0(%r4) 82 ; CHECK: br %r14 83 %ptr = getelementptr i32 *%src, i64 -131073 84 %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst 85 ret i32 %val 86 } 87 88 ; Check that CS does not allow an index. 89 define i32 @f9(i32 %cmp, i32 %swap, i64 %src, i64 %index) { 90 ; CHECK-LABEL: f9: 91 ; CHECK: agr %r4, %r5 92 ; CHECK: cs %r2, %r3, 0(%r4) 93 ; CHECK: br %r14 94 %add1 = add i64 %src, %index 95 %ptr = inttoptr i64 %add1 to i32 * 96 %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst 97 ret i32 %val 98 } 99 100 ; Check that CSY does not allow an index. 101 define i32 @f10(i32 %cmp, i32 %swap, i64 %src, i64 %index) { 102 ; CHECK-LABEL: f10: 103 ; CHECK: agr %r4, %r5 104 ; CHECK: csy %r2, %r3, 4096(%r4) 105 ; CHECK: br %r14 106 %add1 = add i64 %src, %index 107 %add2 = add i64 %add1, 4096 108 %ptr = inttoptr i64 %add2 to i32 * 109 %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst 110 ret i32 %val 111 } 112 113 ; Check that a constant %cmp value is loaded into a register first. 114 define i32 @f11(i32 %dummy, i32 %swap, i32 *%ptr) { 115 ; CHECK-LABEL: f11: 116 ; CHECK: lhi %r2, 1001 117 ; CHECK: cs %r2, %r3, 0(%r4) 118 ; CHECK: br %r14 119 %val = cmpxchg i32 *%ptr, i32 1001, i32 %swap seq_cst 120 ret i32 %val 121 } 122 123 ; Check that a constant %swap value is loaded into a register first. 124 define i32 @f12(i32 %cmp, i32 *%ptr) { 125 ; CHECK-LABEL: f12: 126 ; CHECK: lhi [[SWAP:%r[0-9]+]], 1002 127 ; CHECK: cs %r2, [[SWAP]], 0(%r3) 128 ; CHECK: br %r14 129 %val = cmpxchg i32 *%ptr, i32 %cmp, i32 1002 seq_cst 130 ret i32 %val 131 } 132
