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      1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file is part of the X86 Disassembler Emitter.
     11 // It contains the implementation of the disassembler tables.
     12 // Documentation for the disassembler emitter in general can be found in
     13 //  X86DisasemblerEmitter.h.
     14 //
     15 //===----------------------------------------------------------------------===//
     16 
     17 #include "X86DisassemblerTables.h"
     18 #include "X86DisassemblerShared.h"
     19 #include "llvm/ADT/STLExtras.h"
     20 #include "llvm/Support/ErrorHandling.h"
     21 #include "llvm/Support/Format.h"
     22 #include "llvm/TableGen/TableGenBackend.h"
     23 #include <map>
     24 
     25 using namespace llvm;
     26 using namespace X86Disassembler;
     27 
     28 /// inheritsFrom - Indicates whether all instructions in one class also belong
     29 ///   to another class.
     30 ///
     31 /// @param child  - The class that may be the subset
     32 /// @param parent - The class that may be the superset
     33 /// @return       - True if child is a subset of parent, false otherwise.
     34 static inline bool inheritsFrom(InstructionContext child,
     35                                 InstructionContext parent,
     36                                 bool VEX_LIG = false) {
     37   if (child == parent)
     38     return true;
     39 
     40   switch (parent) {
     41   case IC:
     42     return(inheritsFrom(child, IC_64BIT) ||
     43            inheritsFrom(child, IC_OPSIZE) ||
     44            inheritsFrom(child, IC_ADSIZE) ||
     45            inheritsFrom(child, IC_XD) ||
     46            inheritsFrom(child, IC_XS));
     47   case IC_64BIT:
     48     return(inheritsFrom(child, IC_64BIT_REXW)   ||
     49            inheritsFrom(child, IC_64BIT_OPSIZE) ||
     50            inheritsFrom(child, IC_64BIT_ADSIZE) ||
     51            inheritsFrom(child, IC_64BIT_XD)     ||
     52            inheritsFrom(child, IC_64BIT_XS));
     53   case IC_OPSIZE:
     54     return inheritsFrom(child, IC_64BIT_OPSIZE);
     55   case IC_ADSIZE:
     56   case IC_64BIT_ADSIZE:
     57     return false;
     58   case IC_XD:
     59     return inheritsFrom(child, IC_64BIT_XD);
     60   case IC_XS:
     61     return inheritsFrom(child, IC_64BIT_XS);
     62   case IC_XD_OPSIZE:
     63     return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
     64   case IC_XS_OPSIZE:
     65     return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
     66   case IC_64BIT_REXW:
     67     return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
     68            inheritsFrom(child, IC_64BIT_REXW_XD) ||
     69            inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
     70   case IC_64BIT_OPSIZE:
     71     return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
     72   case IC_64BIT_XD:
     73     return(inheritsFrom(child, IC_64BIT_REXW_XD));
     74   case IC_64BIT_XS:
     75     return(inheritsFrom(child, IC_64BIT_REXW_XS));
     76   case IC_64BIT_XD_OPSIZE:
     77   case IC_64BIT_XS_OPSIZE:
     78     return false;
     79   case IC_64BIT_REXW_XD:
     80   case IC_64BIT_REXW_XS:
     81   case IC_64BIT_REXW_OPSIZE:
     82     return false;
     83   case IC_VEX:
     84     return inheritsFrom(child, IC_VEX_L_W) ||
     85            inheritsFrom(child, IC_VEX_W) ||
     86            (VEX_LIG && inheritsFrom(child, IC_VEX_L));
     87   case IC_VEX_XS:
     88     return inheritsFrom(child, IC_VEX_L_W_XS) ||
     89            inheritsFrom(child, IC_VEX_W_XS) ||
     90            (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
     91   case IC_VEX_XD:
     92     return inheritsFrom(child, IC_VEX_L_W_XD) ||
     93            inheritsFrom(child, IC_VEX_W_XD) ||
     94            (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
     95   case IC_VEX_OPSIZE:
     96     return inheritsFrom(child, IC_VEX_L_W_OPSIZE) ||
     97            inheritsFrom(child, IC_VEX_W_OPSIZE) ||
     98            (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
     99   case IC_VEX_W:
    100   case IC_VEX_W_XS:
    101   case IC_VEX_W_XD:
    102   case IC_VEX_W_OPSIZE:
    103     return false;
    104   case IC_VEX_L:
    105   case IC_VEX_L_XS:
    106   case IC_VEX_L_XD:
    107   case IC_VEX_L_OPSIZE:
    108     return false;
    109   case IC_VEX_L_W:
    110   case IC_VEX_L_W_XS:
    111   case IC_VEX_L_W_XD:
    112   case IC_VEX_L_W_OPSIZE:
    113     return false;
    114   case IC_EVEX:
    115     return inheritsFrom(child, IC_EVEX_W) ||
    116            inheritsFrom(child, IC_EVEX_L_W);
    117   case IC_EVEX_XS:
    118     return inheritsFrom(child, IC_EVEX_W_XS) ||
    119            inheritsFrom(child, IC_EVEX_L_W_XS);
    120   case IC_EVEX_XD:
    121     return inheritsFrom(child, IC_EVEX_W_XD) ||
    122            inheritsFrom(child, IC_EVEX_L_W_XD);
    123   case IC_EVEX_OPSIZE:
    124     return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
    125            inheritsFrom(child, IC_EVEX_W_OPSIZE);
    126   case IC_EVEX_W:
    127   case IC_EVEX_W_XS:
    128   case IC_EVEX_W_XD:
    129   case IC_EVEX_W_OPSIZE:
    130     return false;
    131   case IC_EVEX_L:
    132   case IC_EVEX_L_XS:
    133   case IC_EVEX_L_XD:
    134   case IC_EVEX_L_OPSIZE:
    135     return false;
    136   case IC_EVEX_L_W:
    137   case IC_EVEX_L_W_XS:
    138   case IC_EVEX_L_W_XD:
    139   case IC_EVEX_L_W_OPSIZE:
    140     return false;
    141   case IC_EVEX_L2:
    142   case IC_EVEX_L2_XS:
    143   case IC_EVEX_L2_XD:
    144   case IC_EVEX_L2_OPSIZE:
    145     return false;
    146   case IC_EVEX_L2_W:
    147   case IC_EVEX_L2_W_XS:
    148   case IC_EVEX_L2_W_XD:
    149   case IC_EVEX_L2_W_OPSIZE:
    150     return false;
    151   case IC_EVEX_K:
    152     return inheritsFrom(child, IC_EVEX_W_K) ||
    153            inheritsFrom(child, IC_EVEX_L_W_K);
    154   case IC_EVEX_XS_K:
    155     return inheritsFrom(child, IC_EVEX_W_XS_K) ||
    156            inheritsFrom(child, IC_EVEX_L_W_XS_K);
    157   case IC_EVEX_XD_K:
    158     return inheritsFrom(child, IC_EVEX_W_XD_K) ||
    159            inheritsFrom(child, IC_EVEX_L_W_XD_K);
    160   case IC_EVEX_OPSIZE_K:
    161     return inheritsFrom(child, IC_EVEX_W_OPSIZE_K) ||
    162            inheritsFrom(child, IC_EVEX_W_OPSIZE_K);
    163   case IC_EVEX_W_K:
    164   case IC_EVEX_W_XS_K:
    165   case IC_EVEX_W_XD_K:
    166   case IC_EVEX_W_OPSIZE_K:
    167     return false;
    168   case IC_EVEX_L_K:
    169   case IC_EVEX_L_XS_K:
    170   case IC_EVEX_L_XD_K:
    171   case IC_EVEX_L_OPSIZE_K:
    172     return false;
    173   case IC_EVEX_L_W_K:
    174   case IC_EVEX_L_W_XS_K:
    175   case IC_EVEX_L_W_XD_K:
    176   case IC_EVEX_L_W_OPSIZE_K:
    177     return false;
    178   case IC_EVEX_L2_K:
    179   case IC_EVEX_L2_B:
    180   case IC_EVEX_L2_XS_K:
    181   case IC_EVEX_L2_XD_K:
    182   case IC_EVEX_L2_OPSIZE_K:
    183   case IC_EVEX_L2_OPSIZE_B:
    184     return false;
    185   case IC_EVEX_L2_W_K:
    186   case IC_EVEX_L2_W_XS_K:
    187   case IC_EVEX_L2_W_XD_K:
    188   case IC_EVEX_L2_W_OPSIZE_K:
    189   case IC_EVEX_L2_W_OPSIZE_B:
    190     return false;
    191   default:
    192     llvm_unreachable("Unknown instruction class");
    193   }
    194 }
    195 
    196 /// outranks - Indicates whether, if an instruction has two different applicable
    197 ///   classes, which class should be preferred when performing decode.  This
    198 ///   imposes a total ordering (ties are resolved toward "lower")
    199 ///
    200 /// @param upper  - The class that may be preferable
    201 /// @param lower  - The class that may be less preferable
    202 /// @return       - True if upper is to be preferred, false otherwise.
    203 static inline bool outranks(InstructionContext upper,
    204                             InstructionContext lower) {
    205   assert(upper < IC_max);
    206   assert(lower < IC_max);
    207 
    208 #define ENUM_ENTRY(n, r, d) r,
    209 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
    210   ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
    211   static int ranks[IC_max] = {
    212     INSTRUCTION_CONTEXTS
    213   };
    214 #undef ENUM_ENTRY
    215 #undef ENUM_ENTRY_K_B
    216 
    217   return (ranks[upper] > ranks[lower]);
    218 }
    219 
    220 /// stringForContext - Returns a string containing the name of a particular
    221 ///   InstructionContext, usually for diagnostic purposes.
    222 ///
    223 /// @param insnContext  - The instruction class to transform to a string.
    224 /// @return           - A statically-allocated string constant that contains the
    225 ///                     name of the instruction class.
    226 static inline const char* stringForContext(InstructionContext insnContext) {
    227   switch (insnContext) {
    228   default:
    229     llvm_unreachable("Unhandled instruction class");
    230 #define ENUM_ENTRY(n, r, d)   case n: return #n; break;
    231 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
    232         ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
    233   INSTRUCTION_CONTEXTS
    234 #undef ENUM_ENTRY
    235 #undef ENUM_ENTRY_K_B
    236   }
    237 }
    238 
    239 /// stringForOperandType - Like stringForContext, but for OperandTypes.
    240 static inline const char* stringForOperandType(OperandType type) {
    241   switch (type) {
    242   default:
    243     llvm_unreachable("Unhandled type");
    244 #define ENUM_ENTRY(i, d) case i: return #i;
    245   TYPES
    246 #undef ENUM_ENTRY
    247   }
    248 }
    249 
    250 /// stringForOperandEncoding - like stringForContext, but for
    251 ///   OperandEncodings.
    252 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
    253   switch (encoding) {
    254   default:
    255     llvm_unreachable("Unhandled encoding");
    256 #define ENUM_ENTRY(i, d) case i: return #i;
    257   ENCODINGS
    258 #undef ENUM_ENTRY
    259   }
    260 }
    261 
    262 void DisassemblerTables::emitOneID(raw_ostream &o, unsigned &i, InstrUID id,
    263                                    bool addComma) const {
    264   if (id)
    265     o.indent(i * 2) << format("0x%hx", id);
    266   else
    267     o.indent(i * 2) << 0;
    268 
    269   if (addComma)
    270     o << ", ";
    271   else
    272     o << "  ";
    273 
    274   o << "/* ";
    275   o << InstructionSpecifiers[id].name;
    276   o << "*/";
    277 
    278   o << "\n";
    279 }
    280 
    281 /// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by
    282 ///   all ModR/M decisions for instructions that are invalid for all possible
    283 ///   ModR/M byte values.
    284 ///
    285 /// @param o        - The output stream on which to emit the table.
    286 /// @param i        - The indentation level for that output stream.
    287 static void emitEmptyTable(raw_ostream &o, unsigned &i) {
    288   o.indent(i * 2) << "0x0, /* EmptyTable */\n";
    289 }
    290 
    291 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
    292 ///   be compacted by eliminating redundant information.
    293 ///
    294 /// @param decision - The decision to be compacted.
    295 /// @return         - The compactest available representation for the decision.
    296 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
    297   bool satisfiesOneEntry = true;
    298   bool satisfiesSplitRM = true;
    299   bool satisfiesSplitReg = true;
    300   bool satisfiesSplitMisc = true;
    301 
    302   for (unsigned index = 0; index < 256; ++index) {
    303     if (decision.instructionIDs[index] != decision.instructionIDs[0])
    304       satisfiesOneEntry = false;
    305 
    306     if (((index & 0xc0) == 0xc0) &&
    307        (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
    308       satisfiesSplitRM = false;
    309 
    310     if (((index & 0xc0) != 0xc0) &&
    311        (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
    312       satisfiesSplitRM = false;
    313 
    314     if (((index & 0xc0) == 0xc0) &&
    315        (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
    316       satisfiesSplitReg = false;
    317 
    318     if (((index & 0xc0) != 0xc0) &&
    319        (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
    320       satisfiesSplitMisc = false;
    321   }
    322 
    323   if (satisfiesOneEntry)
    324     return MODRM_ONEENTRY;
    325 
    326   if (satisfiesSplitRM)
    327     return MODRM_SPLITRM;
    328 
    329   if (satisfiesSplitReg && satisfiesSplitMisc)
    330     return MODRM_SPLITREG;
    331 
    332   if (satisfiesSplitMisc)
    333     return MODRM_SPLITMISC;
    334 
    335   return MODRM_FULL;
    336 }
    337 
    338 /// stringForDecisionType - Returns a statically-allocated string corresponding
    339 ///   to a particular decision type.
    340 ///
    341 /// @param dt - The decision type.
    342 /// @return   - A pointer to the statically-allocated string (e.g.,
    343 ///             "MODRM_ONEENTRY" for MODRM_ONEENTRY).
    344 static const char* stringForDecisionType(ModRMDecisionType dt) {
    345 #define ENUM_ENTRY(n) case n: return #n;
    346   switch (dt) {
    347     default:
    348       llvm_unreachable("Unknown decision type");
    349     MODRMTYPES
    350   };
    351 #undef ENUM_ENTRY
    352 }
    353 
    354 /// stringForModifierType - Returns a statically-allocated string corresponding
    355 ///   to an opcode modifier type.
    356 ///
    357 /// @param mt - The modifier type.
    358 /// @return   - A pointer to the statically-allocated string (e.g.,
    359 ///             "MODIFIER_NONE" for MODIFIER_NONE).
    360 static const char* stringForModifierType(ModifierType mt) {
    361 #define ENUM_ENTRY(n) case n: return #n;
    362   switch(mt) {
    363     default:
    364       llvm_unreachable("Unknown modifier type");
    365     MODIFIER_TYPES
    366   };
    367 #undef ENUM_ENTRY
    368 }
    369 
    370 DisassemblerTables::DisassemblerTables() {
    371   unsigned i;
    372 
    373   for (i = 0; i < array_lengthof(Tables); i++) {
    374     Tables[i] = new ContextDecision;
    375     memset(Tables[i], 0, sizeof(ContextDecision));
    376   }
    377 
    378   HasConflicts = false;
    379 }
    380 
    381 DisassemblerTables::~DisassemblerTables() {
    382   unsigned i;
    383 
    384   for (i = 0; i < array_lengthof(Tables); i++)
    385     delete Tables[i];
    386 }
    387 
    388 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
    389                                            unsigned &i1, unsigned &i2,
    390                                            ModRMDecision &decision) const {
    391   static uint32_t sTableNumber = 0;
    392   static uint32_t sEntryNumber = 1;
    393   ModRMDecisionType dt = getDecisionType(decision);
    394 
    395   if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
    396   {
    397     o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
    398     i2++;
    399 
    400     o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
    401     o2.indent(i2) << 0 << " /* EmptyTable */\n";
    402 
    403     i2--;
    404     o2.indent(i2) << "}";
    405     return;
    406   }
    407 
    408   o1 << "/* Table" << sTableNumber << " */\n";
    409   i1++;
    410 
    411   switch (dt) {
    412     default:
    413       llvm_unreachable("Unknown decision type");
    414     case MODRM_ONEENTRY:
    415       emitOneID(o1, i1, decision.instructionIDs[0], true);
    416       break;
    417     case MODRM_SPLITRM:
    418       emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00
    419       emitOneID(o1, i1, decision.instructionIDs[0xc0], true); // mod = 0b11
    420       break;
    421     case MODRM_SPLITREG:
    422       for (unsigned index = 0; index < 64; index += 8)
    423         emitOneID(o1, i1, decision.instructionIDs[index], true);
    424       for (unsigned index = 0xc0; index < 256; index += 8)
    425         emitOneID(o1, i1, decision.instructionIDs[index], true);
    426       break;
    427     case MODRM_SPLITMISC:
    428       for (unsigned index = 0; index < 64; index += 8)
    429         emitOneID(o1, i1, decision.instructionIDs[index], true);
    430       for (unsigned index = 0xc0; index < 256; ++index)
    431         emitOneID(o1, i1, decision.instructionIDs[index], true);
    432       break;
    433     case MODRM_FULL:
    434       for (unsigned index = 0; index < 256; ++index)
    435         emitOneID(o1, i1, decision.instructionIDs[index], true);
    436       break;
    437   }
    438 
    439   i1--;
    440 
    441   o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
    442   i2++;
    443 
    444   o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
    445   o2.indent(i2) << sEntryNumber << " /* Table" << sTableNumber << " */\n";
    446 
    447   i2--;
    448   o2.indent(i2) << "}";
    449 
    450   switch (dt) {
    451     default:
    452       llvm_unreachable("Unknown decision type");
    453     case MODRM_ONEENTRY:
    454       sEntryNumber += 1;
    455       break;
    456     case MODRM_SPLITRM:
    457       sEntryNumber += 2;
    458       break;
    459     case MODRM_SPLITREG:
    460       sEntryNumber += 16;
    461       break;
    462     case MODRM_SPLITMISC:
    463       sEntryNumber += 8 + 64;
    464       break;
    465     case MODRM_FULL:
    466       sEntryNumber += 256;
    467       break;
    468   }
    469 
    470   // We assume that the index can fit into uint16_t.
    471   assert(sEntryNumber < 65536U &&
    472          "Index into ModRMDecision is too large for uint16_t!");
    473 
    474   ++sTableNumber;
    475 }
    476 
    477 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
    478                                             unsigned &i1, unsigned &i2,
    479                                             OpcodeDecision &decision) const {
    480   o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
    481   i2++;
    482   o2.indent(i2) << "{" << "\n";
    483   i2++;
    484 
    485   for (unsigned index = 0; index < 256; ++index) {
    486     o2.indent(i2);
    487 
    488     o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
    489 
    490     emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]);
    491 
    492     if (index <  255)
    493       o2 << ",";
    494 
    495     o2 << "\n";
    496   }
    497 
    498   i2--;
    499   o2.indent(i2) << "}" << "\n";
    500   i2--;
    501   o2.indent(i2) << "}" << "\n";
    502 }
    503 
    504 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
    505                                              unsigned &i1, unsigned &i2,
    506                                              ContextDecision &decision,
    507                                              const char* name) const {
    508   o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
    509   i2++;
    510   o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
    511   i2++;
    512 
    513   for (unsigned index = 0; index < IC_max; ++index) {
    514     o2.indent(i2) << "/* ";
    515     o2 << stringForContext((InstructionContext)index);
    516     o2 << " */";
    517     o2 << "\n";
    518 
    519     emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]);
    520 
    521     if (index + 1 < IC_max)
    522       o2 << ", ";
    523   }
    524 
    525   i2--;
    526   o2.indent(i2) << "}" << "\n";
    527   i2--;
    528   o2.indent(i2) << "};" << "\n";
    529 }
    530 
    531 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
    532                                              unsigned &i) const {
    533   unsigned NumInstructions = InstructionSpecifiers.size();
    534 
    535   o << "static const struct OperandSpecifier x86OperandSets[]["
    536     << X86_MAX_OPERANDS << "] = {\n";
    537 
    538   typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
    539   std::map<OperandListTy, unsigned> OperandSets;
    540 
    541   unsigned OperandSetNum = 0;
    542   for (unsigned Index = 0; Index < NumInstructions; ++Index) {
    543     OperandListTy OperandList;
    544 
    545     for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
    546          ++OperandIndex) {
    547       const char *Encoding =
    548         stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
    549                                  .operands[OperandIndex].encoding);
    550       const char *Type =
    551         stringForOperandType((OperandType)InstructionSpecifiers[Index]
    552                              .operands[OperandIndex].type);
    553       OperandList.push_back(std::make_pair(Encoding, Type));
    554     }
    555     unsigned &N = OperandSets[OperandList];
    556     if (N != 0) continue;
    557 
    558     N = ++OperandSetNum;
    559 
    560     o << "  { /* " << (OperandSetNum - 1) << " */\n";
    561     for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
    562       o << "    { " << OperandList[i].first << ", "
    563         << OperandList[i].second << " },\n";
    564     }
    565     o << "  },\n";
    566   }
    567   o << "};" << "\n\n";
    568 
    569   o.indent(i * 2) << "static const struct InstructionSpecifier ";
    570   o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
    571 
    572   i++;
    573 
    574   for (unsigned index = 0; index < NumInstructions; ++index) {
    575     o.indent(i * 2) << "{ /* " << index << " */" << "\n";
    576     i++;
    577 
    578     o.indent(i * 2) << stringForModifierType(
    579                        (ModifierType)InstructionSpecifiers[index].modifierType);
    580     o << ",\n";
    581 
    582     o.indent(i * 2) << "0x";
    583     o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
    584     o << ",\n";
    585 
    586     OperandListTy OperandList;
    587     for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
    588          ++OperandIndex) {
    589       const char *Encoding =
    590         stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
    591                                  .operands[OperandIndex].encoding);
    592       const char *Type =
    593         stringForOperandType((OperandType)InstructionSpecifiers[index]
    594                              .operands[OperandIndex].type);
    595       OperandList.push_back(std::make_pair(Encoding, Type));
    596     }
    597     o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
    598 
    599     o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
    600     o << "\n";
    601 
    602     i--;
    603     o.indent(i * 2) << "}";
    604 
    605     if (index + 1 < NumInstructions)
    606       o << ",";
    607 
    608     o << "\n";
    609   }
    610 
    611   i--;
    612   o.indent(i * 2) << "};" << "\n";
    613 }
    614 
    615 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
    616   o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
    617                      "[256] = {\n";
    618   i++;
    619 
    620   for (unsigned index = 0; index < 256; ++index) {
    621     o.indent(i * 2);
    622 
    623     if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
    624       o << "IC_VEX_L_W_OPSIZE";
    625     else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
    626       o << "IC_VEX_L_OPSIZE";
    627     else if ((index & ATTR_VEXL) && (index & ATTR_XD))
    628       o << "IC_VEX_L_XD";
    629     else if ((index & ATTR_VEXL) && (index & ATTR_XS))
    630       o << "IC_VEX_L_XS";
    631     else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
    632       o << "IC_VEX_W_OPSIZE";
    633     else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
    634       o << "IC_VEX_W_XD";
    635     else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
    636       o << "IC_VEX_W_XS";
    637     else if (index & ATTR_VEXL)
    638       o << "IC_VEX_L";
    639     else if ((index & ATTR_VEX) && (index & ATTR_REXW))
    640       o << "IC_VEX_W";
    641     else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
    642       o << "IC_VEX_OPSIZE";
    643     else if ((index & ATTR_VEX) && (index & ATTR_XD))
    644       o << "IC_VEX_XD";
    645     else if ((index & ATTR_VEX) && (index & ATTR_XS))
    646       o << "IC_VEX_XS";
    647     else if (index & ATTR_VEX)
    648       o << "IC_VEX";
    649     else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
    650       o << "IC_64BIT_REXW_XS";
    651     else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
    652       o << "IC_64BIT_REXW_XD";
    653     else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
    654              (index & ATTR_OPSIZE))
    655       o << "IC_64BIT_REXW_OPSIZE";
    656     else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
    657       o << "IC_64BIT_XD_OPSIZE";
    658     else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
    659       o << "IC_64BIT_XS_OPSIZE";
    660     else if ((index & ATTR_64BIT) && (index & ATTR_XS))
    661       o << "IC_64BIT_XS";
    662     else if ((index & ATTR_64BIT) && (index & ATTR_XD))
    663       o << "IC_64BIT_XD";
    664     else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
    665       o << "IC_64BIT_OPSIZE";
    666     else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
    667       o << "IC_64BIT_ADSIZE";
    668     else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
    669       o << "IC_64BIT_REXW";
    670     else if ((index & ATTR_64BIT))
    671       o << "IC_64BIT";
    672     else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
    673       o << "IC_XS_OPSIZE";
    674     else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
    675       o << "IC_XD_OPSIZE";
    676     else if (index & ATTR_XS)
    677       o << "IC_XS";
    678     else if (index & ATTR_XD)
    679       o << "IC_XD";
    680     else if (index & ATTR_OPSIZE)
    681       o << "IC_OPSIZE";
    682     else if (index & ATTR_ADSIZE)
    683       o << "IC_ADSIZE";
    684     else
    685       o << "IC";
    686 
    687     if (index < 255)
    688       o << ",";
    689     else
    690       o << " ";
    691 
    692     o << " /* " << index << " */";
    693 
    694     o << "\n";
    695   }
    696 
    697   i--;
    698   o.indent(i * 2) << "};" << "\n";
    699 }
    700 
    701 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
    702                                              unsigned &i1, unsigned &i2) const {
    703   emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR);
    704   emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR);
    705   emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR);
    706   emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR);
    707   emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR);
    708   emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR);
    709 }
    710 
    711 void DisassemblerTables::emit(raw_ostream &o) const {
    712   unsigned i1 = 0;
    713   unsigned i2 = 0;
    714 
    715   std::string s1;
    716   std::string s2;
    717 
    718   raw_string_ostream o1(s1);
    719   raw_string_ostream o2(s2);
    720 
    721   emitInstructionInfo(o, i2);
    722   o << "\n";
    723 
    724   emitContextTable(o, i2);
    725   o << "\n";
    726 
    727   o << "static const InstrUID modRMTable[] = {\n";
    728   i1++;
    729   emitEmptyTable(o1, i1);
    730   i1--;
    731   emitContextDecisions(o1, o2, i1, i2);
    732 
    733   o << o1.str();
    734   o << "  0x0\n";
    735   o << "};\n";
    736   o << "\n";
    737   o << o2.str();
    738   o << "\n";
    739   o << "\n";
    740 }
    741 
    742 void DisassemblerTables::setTableFields(ModRMDecision     &decision,
    743                                         const ModRMFilter &filter,
    744                                         InstrUID          uid,
    745                                         uint8_t           opcode) {
    746   for (unsigned index = 0; index < 256; ++index) {
    747     if (filter.accepts(index)) {
    748       if (decision.instructionIDs[index] == uid)
    749         continue;
    750 
    751       if (decision.instructionIDs[index] != 0) {
    752         InstructionSpecifier &newInfo =
    753           InstructionSpecifiers[uid];
    754         InstructionSpecifier &previousInfo =
    755           InstructionSpecifiers[decision.instructionIDs[index]];
    756 
    757         if(newInfo.filtered)
    758           continue; // filtered instructions get lowest priority
    759 
    760         if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
    761                                            newInfo.name == "XCHG32ar" ||
    762                                            newInfo.name == "XCHG32ar64" ||
    763                                            newInfo.name == "XCHG64ar"))
    764           continue; // special case for XCHG*ar and NOOP
    765 
    766         if (outranks(previousInfo.insnContext, newInfo.insnContext))
    767           continue;
    768 
    769         if (previousInfo.insnContext == newInfo.insnContext &&
    770             !previousInfo.filtered) {
    771           errs() << "Error: Primary decode conflict: ";
    772           errs() << newInfo.name << " would overwrite " << previousInfo.name;
    773           errs() << "\n";
    774           errs() << "ModRM   " << index << "\n";
    775           errs() << "Opcode  " << (uint16_t)opcode << "\n";
    776           errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
    777           HasConflicts = true;
    778         }
    779       }
    780 
    781       decision.instructionIDs[index] = uid;
    782     }
    783   }
    784 }
    785 
    786 void DisassemblerTables::setTableFields(OpcodeType          type,
    787                                         InstructionContext  insnContext,
    788                                         uint8_t             opcode,
    789                                         const ModRMFilter   &filter,
    790                                         InstrUID            uid,
    791                                         bool                is32bit,
    792                                         bool                ignoresVEX_L) {
    793   ContextDecision &decision = *Tables[type];
    794 
    795   for (unsigned index = 0; index < IC_max; ++index) {
    796     if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
    797       continue;
    798 
    799     if (inheritsFrom((InstructionContext)index,
    800                      InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
    801       setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],
    802                      filter,
    803                      uid,
    804                      opcode);
    805   }
    806 }
    807