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      1 #PPC64 PowerPC970 events
      2 #
      3 #  Within each group the event names must be unique.  Each event in a group is
      4 #  assigned to a unique counter.  The groups are from the groups defined in the
      5 #  Performance Monitor Unit user guide for this processor.
      6 #
      7 #  Only events within the same group can be selected simultaneously.
      8 #  Each event is given a unique event number.  The event number is used by the
      9 #  OProfile code to resolve event names for the post-processing.  This is done
     10 #  to preserve compatibility with the rest of the OProfile code.  The event
     11 #  numbers are formatted as follows: <group_num>concat(<counter for the event>).
     12 
     13 #Group Default
     14 event:0X001 counters:1 um:zero minimum:10000 name:CYCLES : Processor Cycles
     15 
     16 
     17 #Group 1 pm_slice0, Time Slice 0
     18 event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_slice0) Run cycles
     19 event:0X011 counters:1 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
     20 event:0X012 counters:2 um:zero minimum:1000 name:PM_STOP_COMPLETION_GRP1 : (Group 1 pm_slice0) Completion stopped
     21 event:0X013 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_slice0) Instructions completed
     22 event:0X014 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP1 : (Group 1 pm_slice0) One or more PPC instruction completed
     23 event:0X015 counters:5 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
     24 event:0X016 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP1 : (Group 1 pm_slice0) Group completed
     25 event:0X017 counters:7 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP1 : (Group 1 pm_slice0) Group dispatch rejected
     26 
     27 #Group 2 pm_eprof, Group for use with eprof
     28 event:0X020 counters:0 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
     29 event:0X021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
     30 event:0X022 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load misses
     31 event:0X023 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP2 : (Group 2 pm_eprof) L1 D cache entries invalidated from L2
     32 event:0X024 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP2 : (Group 2 pm_eprof) Instructions dispatched
     33 event:0X025 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP2 : (Group 2 pm_eprof) Instructions completed
     34 event:0X026 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP2 : (Group 2 pm_eprof) L1 D cache store references
     35 event:0X027 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load references
     36 
     37 #Group 3 pm_basic, Basic performance indicators
     38 event:0X030 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP3 : (Group 3 pm_basic) Instructions completed
     39 event:0X031 counters:1 um:zero minimum:10000 name:PM_CYC_GRP3 : (Group 3 pm_basic) Processor cycles
     40 event:0X032 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP3 : (Group 3 pm_basic) L1 D cache load misses
     41 event:0X033 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP3 : (Group 3 pm_basic) L1 D cache entries invalidated from L2
     42 event:0X034 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP3 : (Group 3 pm_basic) Instructions dispatched
     43 event:0X035 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP3 : (Group 3 pm_basic) Instructions completed
     44 event:0X036 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP3 : (Group 3 pm_basic) L1 D cache store references
     45 event:0X037 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP3 : (Group 3 pm_basic) L1 D cache load references
     46 
     47 #Group 4 pm_lsu, Information on the Load Store Unit
     48 event:0X040 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_ULD_GRP4 : (Group 4 pm_lsu) LRQ unaligned load flushes
     49 event:0X041 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP4 : (Group 4 pm_lsu) SRQ unaligned store flushes
     50 event:0X042 counters:2 um:zero minimum:10000 name:PM_CYC_GRP4 : (Group 4 pm_lsu) Processor cycles
     51 event:0X043 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP4 : (Group 4 pm_lsu) Instructions completed
     52 event:0X044 counters:4 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_GRP4 : (Group 4 pm_lsu) SRQ flushes
     53 event:0X045 counters:5 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_GRP4 : (Group 4 pm_lsu) LRQ flushes
     54 event:0X046 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP4 : (Group 4 pm_lsu) L1 D cache store references
     55 event:0X047 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP4 : (Group 4 pm_lsu) L1 D cache load references
     56 
     57 #Group 5 pm_fpu1, Floating Point events
     58 event:0X050 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP5 : (Group 5 pm_fpu1) FPU executed FDIV instruction
     59 event:0X051 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP5 : (Group 5 pm_fpu1) FPU executed multiply-add instruction
     60 event:0X052 counters:2 um:zero minimum:1000 name:PM_FPU_FEST_GRP5 : (Group 5 pm_fpu1) FPU executed FEST instruction
     61 event:0X053 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP5 : (Group 5 pm_fpu1) FPU produced a result
     62 event:0X054 counters:4 um:zero minimum:10000 name:PM_CYC_GRP5 : (Group 5 pm_fpu1) Processor cycles
     63 event:0X055 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP5 : (Group 5 pm_fpu1) FPU executed FSQRT instruction
     64 event:0X056 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP5 : (Group 5 pm_fpu1) Instructions completed
     65 event:0X057 counters:7 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP5 : (Group 5 pm_fpu1) FPU executing FMOV or FEST instructions
     66 
     67 #Group 6 pm_fpu2, Floating Point events
     68 event:0X060 counters:0 um:zero minimum:1000 name:PM_FPU_DENORM_GRP6 : (Group 6 pm_fpu2) FPU received denormalized data
     69 event:0X061 counters:1 um:zero minimum:1000 name:PM_FPU_STALL3_GRP6 : (Group 6 pm_fpu2) FPU stalled in pipe3
     70 event:0X062 counters:2 um:zero minimum:10000 name:PM_CYC_GRP6 : (Group 6 pm_fpu2) Processor cycles
     71 event:0X063 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP6 : (Group 6 pm_fpu2) Instructions completed
     72 event:0X064 counters:4 um:zero minimum:1000 name:PM_FPU_ALL_GRP6 : (Group 6 pm_fpu2) FPU executed add, mult, sub, cmp or sel instruction
     73 event:0X065 counters:5 um:zero minimum:1000 name:PM_FPU_STF_GRP6 : (Group 6 pm_fpu2) FPU executed store instruction
     74 event:0X066 counters:6 um:zero minimum:1000 name:PM_FPU_FRSP_FCONV_GRP6 : (Group 6 pm_fpu2) FPU executed FRSP or FCONV instructions
     75 event:0X067 counters:7 um:zero minimum:1000 name:PM_LSU_LDF_GRP6 : (Group 6 pm_fpu2) LSU executed Floating Point load instruction
     76 
     77 #Group 7 pm_isu_rename, ISU Rename Pool Events
     78 event:0X070 counters:0 um:zero minimum:1000 name:PM_XER_MAP_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles XER mapper full
     79 event:0X071 counters:1 um:zero minimum:1000 name:PM_CR_MAP_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles CR logical operation mapper full
     80 event:0X072 counters:2 um:zero minimum:1000 name:PM_CRQ_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles CR issue queue full
     81 event:0X073 counters:3 um:zero minimum:1000 name:PM_GRP_DISP_BLK_SB_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles group dispatch blocked by scoreboard
     82 event:0X074 counters:4 um:zero minimum:1000 name:PM_LR_CTR_MAP_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles LR/CTR mapper full
     83 event:0X075 counters:5 um:zero minimum:1000 name:PM_INST_DISP_GRP7 : (Group 7 pm_isu_rename) Instructions dispatched
     84 event:0X076 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP7 : (Group 7 pm_isu_rename) Instructions completed
     85 event:0X077 counters:7 um:zero minimum:10000 name:PM_CYC_GRP7 : (Group 7 pm_isu_rename) Processor cycles
     86 
     87 #Group 8 pm_isu_queues1, ISU Rename Pool Events
     88 event:0X080 counters:0 um:zero minimum:1000 name:PM_FPU0_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FPU0 issue queue full
     89 event:0X081 counters:1 um:zero minimum:1000 name:PM_FPU1_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FPU1 issue queue full
     90 event:0X082 counters:2 um:zero minimum:1000 name:PM_FXLS0_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FXU0/LS0 queue full
     91 event:0X083 counters:3 um:zero minimum:1000 name:PM_FXLS1_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FXU1/LS1 queue full
     92 event:0X084 counters:4 um:zero minimum:10000 name:PM_CYC_GRP8 : (Group 8 pm_isu_queues1) Processor cycles
     93 event:0X085 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP8 : (Group 8 pm_isu_queues1) Instructions completed
     94 event:0X086 counters:6 um:zero minimum:1000 name:PM_LSU_LRQ_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles LRQ full
     95 event:0X087 counters:7 um:zero minimum:1000 name:PM_LSU_SRQ_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles SRQ full
     96 
     97 #Group 9 pm_isu_flow, ISU Instruction Flow Events
     98 event:0X090 counters:0 um:zero minimum:1000 name:PM_INST_DISP_GRP9 : (Group 9 pm_isu_flow) Instructions dispatched
     99 event:0X091 counters:1 um:zero minimum:10000 name:PM_CYC_GRP9 : (Group 9 pm_isu_flow) Processor cycles
    100 event:0X092 counters:2 um:zero minimum:1000 name:PM_FXU0_FIN_GRP9 : (Group 9 pm_isu_flow) FXU0 produced a result
    101 event:0X093 counters:3 um:zero minimum:1000 name:PM_FXU1_FIN_GRP9 : (Group 9 pm_isu_flow) FXU1 produced a result
    102 event:0X094 counters:4 um:zero minimum:1000 name:PM_GRP_DISP_VALID_GRP9 : (Group 9 pm_isu_flow) Group dispatch valid
    103 event:0X095 counters:5 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP9 : (Group 9 pm_isu_flow) Group dispatch rejected
    104 event:0X096 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP9 : (Group 9 pm_isu_flow) Instructions completed
    105 event:0X097 counters:7 um:zero minimum:10000 name:PM_CYC_GRP9 : (Group 9 pm_isu_flow) Processor cycles
    106 
    107 #Group 10 pm_isu_work, ISU Indicators of Work Blockage
    108 event:0X0A0 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP10 : (Group 10 pm_isu_work) Cycles GCT empty
    109 event:0X0A1 counters:1 um:zero minimum:1000 name:PM_WORK_HELD_GRP10 : (Group 10 pm_isu_work) Work held
    110 event:0X0A2 counters:2 um:zero minimum:1000 name:PM_STOP_COMPLETION_GRP10 : (Group 10 pm_isu_work) Completion stopped
    111 event:0X0A3 counters:3 um:zero minimum:1000 name:PM_EE_OFF_EXT_INT_GRP10 : (Group 10 pm_isu_work) Cycles MSR(EE) bit off and external interrupt pending
    112 event:0X0A4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP10 : (Group 10 pm_isu_work) Processor cycles
    113 event:0X0A5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP10 : (Group 10 pm_isu_work) Instructions completed
    114 event:0X0A6 counters:6 um:zero minimum:1000 name:PM_EE_OFF_GRP10 : (Group 10 pm_isu_work) Cycles MSR(EE) bit off
    115 event:0X0A7 counters:7 um:zero minimum:1000 name:PM_EXT_INT_GRP10 : (Group 10 pm_isu_work) External interrupts
    116 
    117 #Group 11 pm_fpu3, Floating Point events by unit
    118 event:0X0B0 counters:0 um:zero minimum:1000 name:PM_FPU0_FDIV_GRP11 : (Group 11 pm_fpu3) FPU0 executed FDIV instruction
    119 event:0X0B1 counters:1 um:zero minimum:1000 name:PM_FPU1_FDIV_GRP11 : (Group 11 pm_fpu3) FPU1 executed FDIV instruction
    120 event:0X0B2 counters:2 um:zero minimum:1000 name:PM_FPU0_FRSP_FCONV_GRP11 : (Group 11 pm_fpu3) FPU0 executed FRSP or FCONV instructions
    121 event:0X0B3 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP11 : (Group 11 pm_fpu3) FPU1 executed FRSP or FCONV instructions
    122 event:0X0B4 counters:4 um:zero minimum:1000 name:PM_FPU0_FMA_GRP11 : (Group 11 pm_fpu3) FPU0 executed multiply-add instruction
    123 event:0X0B5 counters:5 um:zero minimum:1000 name:PM_FPU1_FMA_GRP11 : (Group 11 pm_fpu3) FPU1 executed multiply-add instruction
    124 event:0X0B6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP11 : (Group 11 pm_fpu3) Instructions completed
    125 event:0X0B7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP11 : (Group 11 pm_fpu3) Processor cycles
    126 
    127 #Group 12 pm_fpu4, Floating Point events by unit
    128 event:0X0C0 counters:0 um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU0 executed FSQRT instruction
    129 event:0X0C1 counters:1 um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU1 executed FSQRT instruction
    130 event:0X0C2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP12 : (Group 12 pm_fpu4) FPU0 produced a result
    131 event:0X0C3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP12 : (Group 12 pm_fpu4) FPU1 produced a result
    132 event:0X0C4 counters:4 um:zero minimum:1000 name:PM_FPU0_ALL_GRP12 : (Group 12 pm_fpu4) FPU0 executed add, mult, sub, cmp or sel instruction
    133 event:0X0C5 counters:5 um:zero minimum:1000 name:PM_FPU1_ALL_GRP12 : (Group 12 pm_fpu4) FPU1 executed add, mult, sub, cmp or sel instruction
    134 event:0X0C6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP12 : (Group 12 pm_fpu4) Instructions completed
    135 event:0X0C7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP12 : (Group 12 pm_fpu4) Processor cycles
    136 
    137 #Group 13 pm_fpu5, Floating Point events by unit
    138 event:0X0D0 counters:0 um:zero minimum:1000 name:PM_FPU0_DENORM_GRP13 : (Group 13 pm_fpu5) FPU0 received denormalized data
    139 event:0X0D1 counters:1 um:zero minimum:1000 name:PM_FPU1_DENORM_GRP13 : (Group 13 pm_fpu5) FPU1 received denormalized data
    140 event:0X0D2 counters:2 um:zero minimum:1000 name:PM_FPU0_FMOV_FEST_GRP13 : (Group 13 pm_fpu5) FPU0 executed FMOV or FEST instructions
    141 event:0X0D3 counters:3 um:zero minimum:1000 name:PM_FPU1_FMOV_FEST_GRP13 : (Group 13 pm_fpu5) FPU1 executing FMOV or FEST instructions
    142 event:0X0D4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP13 : (Group 13 pm_fpu5) Processor cycles
    143 event:0X0D5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP13 : (Group 13 pm_fpu5) Instructions completed
    144 event:0X0D6 counters:6 um:zero minimum:1000 name:PM_FPU0_FEST_GRP13 : (Group 13 pm_fpu5) FPU0 executed FEST instruction
    145 event:0X0D7 counters:7 um:zero minimum:1000 name:PM_FPU1_FEST_GRP13 : (Group 13 pm_fpu5) FPU1 executed FEST instruction
    146 
    147 #Group 14 pm_fpu7, Floating Point events by unit
    148 event:0X0E0 counters:0 um:zero minimum:1000 name:PM_FPU0_STALL3_GRP14 : (Group 14 pm_fpu7) FPU0 stalled in pipe3
    149 event:0X0E1 counters:1 um:zero minimum:1000 name:PM_FPU1_STALL3_GRP14 : (Group 14 pm_fpu7) FPU1 stalled in pipe3
    150 event:0X0E2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP14 : (Group 14 pm_fpu7) FPU0 produced a result
    151 event:0X0E3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP14 : (Group 14 pm_fpu7) FPU1 produced a result
    152 event:0X0E4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP14 : (Group 14 pm_fpu7) Processor cycles
    153 event:0X0E5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP14 : (Group 14 pm_fpu7) Instructions completed
    154 event:0X0E6 counters:6 um:zero minimum:10000 name:PM_CYC_GRP14 : (Group 14 pm_fpu7) Processor cycles
    155 event:0X0E7 counters:7 um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP14 : (Group 14 pm_fpu7) FPU0 executed FPSCR instruction
    156 
    157 #Group 15 pm_lsu_flush, LSU Flush Events
    158 event:0X0F0 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_LRQ_GRP15 : (Group 15 pm_lsu_flush) LSU0 LRQ flushes
    159 event:0X0F1 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_LRQ_GRP15 : (Group 15 pm_lsu_flush) LSU1 LRQ flushes
    160 event:0X0F2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP15 : (Group 15 pm_lsu_flush) Processor cycles
    161 event:0X0F3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP15 : (Group 15 pm_lsu_flush) Processor cycles
    162 event:0X0F4 counters:4 um:zero minimum:1000 name:PM_LSU0_FLUSH_SRQ_GRP15 : (Group 15 pm_lsu_flush) LSU0 SRQ flushes
    163 event:0X0F5 counters:5 um:zero minimum:1000 name:PM_LSU1_FLUSH_SRQ_GRP15 : (Group 15 pm_lsu_flush) LSU1 SRQ flushes
    164 event:0X0F6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP15 : (Group 15 pm_lsu_flush) Instructions completed
    165 event:0X0F7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP15 : (Group 15 pm_lsu_flush) Processor cycles
    166 
    167 #Group 16 pm_lsu_load1, LSU Load Events
    168 event:0X100 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_ULD_GRP16 : (Group 16 pm_lsu_load1) LSU0 unaligned load flushes
    169 event:0X101 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_ULD_GRP16 : (Group 16 pm_lsu_load1) LSU1 unaligned load flushes
    170 event:0X102 counters:2 um:zero minimum:1000 name:PM_LD_REF_L1_LSU0_GRP16 : (Group 16 pm_lsu_load1) LSU0 L1 D cache load references
    171 event:0X103 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_LSU1_GRP16 : (Group 16 pm_lsu_load1) LSU1 L1 D cache load references
    172 event:0X104 counters:4 um:zero minimum:10000 name:PM_CYC_GRP16 : (Group 16 pm_lsu_load1) Processor cycles
    173 event:0X105 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP16 : (Group 16 pm_lsu_load1) Instructions completed
    174 event:0X106 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP16 : (Group 16 pm_lsu_load1) LSU0 L1 D cache load misses
    175 event:0X107 counters:7 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP16 : (Group 16 pm_lsu_load1) LSU1 L1 D cache load misses
    176 
    177 #Group 17 pm_lsu_store1, LSU Store Events
    178 event:0X110 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_UST_GRP17 : (Group 17 pm_lsu_store1) LSU0 unaligned store flushes
    179 event:0X111 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_UST_GRP17 : (Group 17 pm_lsu_store1) LSU1 unaligned store flushes
    180 event:0X112 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_LSU0_GRP17 : (Group 17 pm_lsu_store1) LSU0 L1 D cache store references
    181 event:0X113 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_GRP17 : (Group 17 pm_lsu_store1) LSU1 L1 D cache store references
    182 event:0X114 counters:4 um:zero minimum:10000 name:PM_CYC_GRP17 : (Group 17 pm_lsu_store1) Processor cycles
    183 event:0X115 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP17 : (Group 17 pm_lsu_store1) Instructions completed
    184 event:0X116 counters:6 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP17 : (Group 17 pm_lsu_store1) L1 D cache store misses
    185 event:0X117 counters:7 um:zero minimum:1000 name:PM_DC_INV_L2_GRP17 : (Group 17 pm_lsu_store1) L1 D cache entries invalidated from L2
    186 
    187 #Group 18 pm_lsu_store2, LSU Store Events
    188 event:0X120 counters:0 um:zero minimum:1000 name:PM_LSU0_SRQ_STFWD_GRP18 : (Group 18 pm_lsu_store2) LSU0 SRQ store forwarded
    189 event:0X121 counters:1 um:zero minimum:1000 name:PM_LSU1_SRQ_STFWD_GRP18 : (Group 18 pm_lsu_store2) LSU1 SRQ store forwarded
    190 event:0X122 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_LSU0_GRP18 : (Group 18 pm_lsu_store2) LSU0 L1 D cache store references
    191 event:0X123 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_GRP18 : (Group 18 pm_lsu_store2) LSU1 L1 D cache store references
    192 event:0X124 counters:4 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP18 : (Group 18 pm_lsu_store2) LSU0 busy
    193 event:0X125 counters:5 um:zero minimum:10000 name:PM_CYC_GRP18 : (Group 18 pm_lsu_store2) Processor cycles
    194 event:0X126 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP18 : (Group 18 pm_lsu_store2) Instructions completed
    195 event:0X127 counters:7 um:zero minimum:10000 name:PM_CYC_GRP18 : (Group 18 pm_lsu_store2) Processor cycles
    196 
    197 #Group 19 pm_lsu7, Information on the Load Store Unit
    198 event:0X130 counters:0 um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU0 DERAT misses
    199 event:0X131 counters:1 um:zero minimum:1000 name:PM_LSU1_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU1 DERAT misses
    200 event:0X132 counters:2 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles
    201 event:0X133 counters:3 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles
    202 event:0X134 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP19 : (Group 19 pm_lsu7) Instructions completed
    203 event:0X135 counters:5 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles
    204 event:0X136 counters:6 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP19 : (Group 19 pm_lsu7) L1 reload data source valid
    205 event:0X137 counters:7 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles
    206 
    207 #Group 20 pm_misc, Misc Events for testing
    208 event:0X140 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP20 : (Group 20 pm_misc) Cycles GCT empty
    209 event:0X141 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP20 : (Group 20 pm_misc) Cycles LMQ and SRQ empty
    210 event:0X142 counters:2 um:zero minimum:1000 name:PM_HV_CYC_GRP20 : (Group 20 pm_misc) Hypervisor Cycles
    211 event:0X143 counters:3 um:zero minimum:10000 name:PM_CYC_GRP20 : (Group 20 pm_misc) Processor cycles
    212 event:0X144 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP20 : (Group 20 pm_misc) One or more PPC instruction completed
    213 event:0X145 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP20 : (Group 20 pm_misc) Instructions completed
    214 event:0X146 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP20 : (Group 20 pm_misc) Group completed
    215 event:0X147 counters:7 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP20 : (Group 20 pm_misc) Time Base bit transition
    216 
    217 #Group 21 pm_pe_bench1, PE Benchmarker group for FP analysis
    218 event:0X150 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP21 : (Group 21 pm_pe_bench1) FPU executed FDIV instruction
    219 event:0X151 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP21 : (Group 21 pm_pe_bench1) FPU executed multiply-add instruction
    220 event:0X152 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP21 : (Group 21 pm_pe_bench1) FXU produced a result
    221 event:0X153 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP21 : (Group 21 pm_pe_bench1) FPU produced a result
    222 event:0X154 counters:4 um:zero minimum:10000 name:PM_CYC_GRP21 : (Group 21 pm_pe_bench1) Processor cycles
    223 event:0X155 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP21 : (Group 21 pm_pe_bench1) FPU executed FSQRT instruction
    224 event:0X156 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP21 : (Group 21 pm_pe_bench1) Instructions completed
    225 event:0X157 counters:7 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP21 : (Group 21 pm_pe_bench1) FPU executing FMOV or FEST instructions
    226 
    227 #Group 22 pm_pe_bench4, PE Benchmarker group for L1 and TLB
    228 event:0X160 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Data TLB misses
    229 event:0X161 counters:1 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Instruction TLB misses
    230 event:0X162 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache load misses
    231 event:0X163 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache store misses
    232 event:0X164 counters:4 um:zero minimum:10000 name:PM_CYC_GRP22 : (Group 22 pm_pe_bench4) Processor cycles
    233 event:0X165 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP22 : (Group 22 pm_pe_bench4) Instructions completed
    234 event:0X166 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache store references
    235 event:0X167 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache load references
    236 
    237 #Group 23 pm_hpmcount1, Hpmcount group for L1 and TLB behavior
    238 event:0X170 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP23 : (Group 23 pm_hpmcount1) Data TLB misses
    239 event:0X171 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP23 : (Group 23 pm_hpmcount1) Cycles LMQ and SRQ empty
    240 event:0X172 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache load misses
    241 event:0X173 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache store misses
    242 event:0X174 counters:4 um:zero minimum:10000 name:PM_CYC_GRP23 : (Group 23 pm_hpmcount1) Processor cycles
    243 event:0X175 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP23 : (Group 23 pm_hpmcount1) Instructions completed
    244 event:0X176 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache store references
    245 event:0X177 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache load references
    246 
    247 #Group 24 pm_hpmcount2, Hpmcount group for computation
    248 event:0X180 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP24 : (Group 24 pm_hpmcount2) FPU executed FDIV instruction
    249 event:0X181 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP24 : (Group 24 pm_hpmcount2) FPU executed multiply-add instruction
    250 event:0X182 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP24 : (Group 24 pm_hpmcount2) FPU0 produced a result
    251 event:0X183 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP24 : (Group 24 pm_hpmcount2) FPU1 produced a result
    252 event:0X184 counters:4 um:zero minimum:10000 name:PM_CYC_GRP24 : (Group 24 pm_hpmcount2) Processor cycles
    253 event:0X185 counters:5 um:zero minimum:1000 name:PM_FPU_STF_GRP24 : (Group 24 pm_hpmcount2) FPU executed store instruction
    254 event:0X186 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP24 : (Group 24 pm_hpmcount2) Instructions completed
    255 event:0X187 counters:7 um:zero minimum:1000 name:PM_LSU_LDF_GRP24 : (Group 24 pm_hpmcount2) LSU executed Floating Point load instruction
    256 
    257 #Group 25 pm_l1andbr, L1 misses and branch misspredict analysis
    258 event:0X190 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP25 : (Group 25 pm_l1andbr) Instructions completed
    259 event:0X191 counters:1 um:zero minimum:10000 name:PM_CYC_GRP25 : (Group 25 pm_l1andbr) Processor cycles
    260 event:0X192 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP25 : (Group 25 pm_l1andbr) L1 D cache load misses
    261 event:0X193 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP25 : (Group 25 pm_l1andbr) Branches issued
    262 event:0X194 counters:4 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP25 : (Group 25 pm_l1andbr) LSU0 busy
    263 event:0X195 counters:5 um:zero minimum:10000 name:PM_CYC_GRP25 : (Group 25 pm_l1andbr) Processor cycles
    264 event:0X196 counters:6 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP25 : (Group 25 pm_l1andbr) Branch mispredictions due to CR bit setting
    265 event:0X197 counters:7 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP25 : (Group 25 pm_l1andbr) Branch mispredictions due to target address
    266 
    267 #Group 26 pm_imix, Instruction mix: loads, stores and branches
    268 event:0X1A0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP26 : (Group 26 pm_imix) Instructions completed
    269 event:0X1A1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP26 : (Group 26 pm_imix) Processor cycles
    270 event:0X1A2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP26 : (Group 26 pm_imix) L1 D cache load misses
    271 event:0X1A3 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP26 : (Group 26 pm_imix) Branches issued
    272 event:0X1A4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP26 : (Group 26 pm_imix) Processor cycles
    273 event:0X1A5 counters:5 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP26 : (Group 26 pm_imix) LSU0 busy
    274 event:0X1A6 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP26 : (Group 26 pm_imix) L1 D cache store references
    275 event:0X1A7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP26 : (Group 26 pm_imix) L1 D cache load references
    276 
    277 #Group 27 pm_branch, SLB and branch misspredict analysis
    278 event:0X1B0 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP27 : (Group 27 pm_branch) Run cycles
    279 event:0X1B1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP27 : (Group 27 pm_branch) Data SLB misses
    280 event:0X1B2 counters:2 um:zero minimum:1000 name:PM_BR_ISSUED_GRP27 : (Group 27 pm_branch) Branches issued
    281 event:0X1B3 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP27 : (Group 27 pm_branch) Branch mispredictions due to CR bit setting
    282 event:0X1B4 counters:4 um:zero minimum:1000 name:PM_ISLB_MISS_GRP27 : (Group 27 pm_branch) Instruction SLB misses
    283 event:0X1B5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP27 : (Group 27 pm_branch) Processor cycles
    284 event:0X1B6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP27 : (Group 27 pm_branch) Instructions completed
    285 event:0X1B7 counters:7 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP27 : (Group 27 pm_branch) Branch mispredictions due to target address
    286 
    287 #Group 28 pm_data, data source and LMQ
    288 event:0X1C0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP28 : (Group 28 pm_data) Data loaded from L2
    289 event:0X1C1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP28 : (Group 28 pm_data) Instructions completed
    290 event:0X1C2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP28 : (Group 28 pm_data) Data loaded from memory
    291 event:0X1C3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP28 : (Group 28 pm_data) Processor cycles
    292 event:0X1C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP28 : (Group 28 pm_data) Instructions completed
    293 event:0X1C5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP28 : (Group 28 pm_data) Processor cycles
    294 event:0X1C6 counters:6 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP28 : (Group 28 pm_data) LMQ slot 0 allocated
    295 event:0X1C7 counters:7 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP28 : (Group 28 pm_data) LMQ slot 0 valid
    296 
    297 #Group 29 pm_tlb, TLB and LRQ plus data prefetch
    298 event:0X1D0 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP29 : (Group 29 pm_tlb) Data TLB misses
    299 event:0X1D1 counters:1 um:zero minimum:1000 name:PM_ITLB_MISS_GRP29 : (Group 29 pm_tlb) Instruction TLB misses
    300 event:0X1D2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP29 : (Group 29 pm_tlb) Instructions completed
    301 event:0X1D3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP29 : (Group 29 pm_tlb) Processor cycles
    302 event:0X1D4 counters:4 um:zero minimum:1000 name:PM_LSU_LRQ_S0_ALLOC_GRP29 : (Group 29 pm_tlb) LRQ slot 0 allocated
    303 event:0X1D5 counters:5 um:zero minimum:1000 name:PM_LSU_LRQ_S0_VALID_GRP29 : (Group 29 pm_tlb) LRQ slot 0 valid
    304 event:0X1D6 counters:6 um:zero minimum:1000 name:PM_L1_PREF_GRP29 : (Group 29 pm_tlb) L1 cache data prefetches
    305 event:0X1D7 counters:7 um:zero minimum:1000 name:PM_L2_PREF_GRP29 : (Group 29 pm_tlb) L2 cache prefetches
    306 
    307 #Group 30 pm_isource, inst source and tablewalk
    308 event:0X1E0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP30 : (Group 30 pm_isource) Instructions fetched from L2
    309 event:0X1E1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP30 : (Group 30 pm_isource) Instruction fetched from memory
    310 event:0X1E2 counters:2 um:zero minimum:1000 name:PM_HV_CYC_GRP30 : (Group 30 pm_isource) Hypervisor Cycles
    311 event:0X1E3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP30 : (Group 30 pm_isource) Instructions completed
    312 event:0X1E4 counters:4 um:zero minimum:1000 name:PM_DATA_TABLEWALK_CYC_GRP30 : (Group 30 pm_isource) Cycles doing data tablewalks
    313 event:0X1E5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP30 : (Group 30 pm_isource) Processor cycles
    314 event:0X1E6 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP30 : (Group 30 pm_isource) Group completed
    315 event:0X1E7 counters:7 um:zero minimum:1000 name:PM_DC_INV_L2_GRP30 : (Group 30 pm_isource) L1 D cache entries invalidated from L2
    316 
    317 #Group 31 pm_sync, Sync and SRQ
    318 event:0X1F0 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_S0_ALLOC_GRP31 : (Group 31 pm_sync) SRQ slot 0 allocated
    319 event:0X1F1 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_S0_VALID_GRP31 : (Group 31 pm_sync) SRQ slot 0 valid
    320 event:0X1F2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP31 : (Group 31 pm_sync) L1 D cache load misses
    321 event:0X1F3 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_SYNC_CYC_GRP31 : (Group 31 pm_sync) SRQ sync duration
    322 event:0X1F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP31 : (Group 31 pm_sync) Instructions completed
    323 event:0X1F5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP31 : (Group 31 pm_sync) Instructions completed
    324 event:0X1F6 counters:6 um:zero minimum:10000 name:PM_CYC_GRP31 : (Group 31 pm_sync) Processor cycles
    325 event:0X1F7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP31 : (Group 31 pm_sync) L1 D cache load references
    326 
    327 #Group 32 pm_ierat, IERAT
    328 event:0X200 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP32 : (Group 32 pm_ierat) Instruction fetched from L1
    329 event:0X201 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP32 : (Group 32 pm_ierat) Instructions completed
    330 event:0X202 counters:2 um:zero minimum:1000 name:PM_IERAT_XLATE_WR_GRP32 : (Group 32 pm_ierat) Translation written to ierat
    331 event:0X203 counters:3 um:zero minimum:10000 name:PM_CYC_GRP32 : (Group 32 pm_ierat) Processor cycles
    332 event:0X204 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP32 : (Group 32 pm_ierat) Instructions completed
    333 event:0X205 counters:5 um:zero minimum:10000 name:PM_CYC_GRP32 : (Group 32 pm_ierat) Processor cycles
    334 event:0X206 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP32 : (Group 32 pm_ierat) Instructions completed
    335 event:0X207 counters:7 um:zero minimum:10000 name:PM_CYC_GRP32 : (Group 32 pm_ierat) Processor cycles
    336 
    337 #Group 33 pm_derat, DERAT
    338 event:0X210 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP33 : (Group 33 pm_derat) Cycles GCT empty
    339 event:0X211 counters:1 um:zero minimum:1000 name:PM_GRP_DISP_VALID_GRP33 : (Group 33 pm_derat) Group dispatch valid
    340 event:0X212 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP33 : (Group 33 pm_derat) L1 reload data source valid
    341 event:0X213 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP33 : (Group 33 pm_derat) Instructions completed
    342 event:0X214 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP33 : (Group 33 pm_derat) Instructions dispatched
    343 event:0X215 counters:5 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP33 : (Group 33 pm_derat) DERAT misses
    344 event:0X216 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP33 : (Group 33 pm_derat) L1 D cache store references
    345 event:0X217 counters:7 um:zero minimum:10000 name:PM_CYC_GRP33 : (Group 33 pm_derat) Processor cycles
    346 
    347 #Group 34 pm_mark1, Information on marked instructions
    348 event:0X220 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP34 : (Group 34 pm_mark1) Marked L1 D cache load misses
    349 event:0X221 counters:1 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP34 : (Group 34 pm_mark1) Threshold timeout
    350 event:0X222 counters:2 um:zero minimum:10000 name:PM_CYC_GRP34 : (Group 34 pm_mark1) Processor cycles
    351 event:0X223 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP34 : (Group 34 pm_mark1) Marked group completed
    352 event:0X224 counters:4 um:zero minimum:1000 name:PM_GRP_MRK_GRP34 : (Group 34 pm_mark1) Group marked in IDU
    353 event:0X225 counters:5 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP34 : (Group 34 pm_mark1) Marked group issued
    354 event:0X226 counters:6 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP34 : (Group 34 pm_mark1) Marked instruction finished
    355 event:0X227 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP34 : (Group 34 pm_mark1) Instructions completed
    356 
    357 #Group 35 pm_mark2, Marked Instructions Processing Flow
    358 event:0X230 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP35 : (Group 35 pm_mark2) Marked group dispatched
    359 event:0X231 counters:1 um:zero minimum:1000 name:PM_MRK_BRU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction BRU processing finished
    360 event:0X232 counters:2 um:zero minimum:10000 name:PM_CYC_GRP35 : (Group 35 pm_mark2) Processor cycles
    361 event:0X233 counters:3 um:zero minimum:1000 name:PM_MRK_CRU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction CRU processing finished
    362 event:0X234 counters:4 um:zero minimum:1000 name:PM_GRP_MRK_GRP35 : (Group 35 pm_mark2) Group marked in IDU
    363 event:0X235 counters:5 um:zero minimum:1000 name:PM_MRK_FXU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction FXU processing finished
    364 event:0X236 counters:6 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction FPU processing finished
    365 event:0X237 counters:7 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction LSU processing finished
    366 
    367 #Group 36 pm_mark3, Marked Stores Processing Flow
    368 event:0X240 counters:0 um:zero minimum:1000 name:PM_MRK_ST_CMPL_GRP36 : (Group 36 pm_mark3) Marked store instruction completed
    369 event:0X241 counters:1 um:zero minimum:10000 name:PM_CYC_GRP36 : (Group 36 pm_mark3) Processor cycles
    370 event:0X242 counters:2 um:zero minimum:1000 name:PM_MRK_ST_CMPL_INT_GRP36 : (Group 36 pm_mark3) Marked store completed with intervention
    371 event:0X243 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP36 : (Group 36 pm_mark3) Marked group completed
    372 event:0X244 counters:4 um:zero minimum:1000 name:PM_MRK_GRP_TIMEO_GRP36 : (Group 36 pm_mark3) Marked group completion timeout
    373 event:0X245 counters:5 um:zero minimum:1000 name:PM_MRK_ST_GPS_GRP36 : (Group 36 pm_mark3) Marked store sent to GPS
    374 event:0X246 counters:6 um:zero minimum:1000 name:PM_MRK_LSU_SRQ_INST_VALID_GRP36 : (Group 36 pm_mark3) Marked instruction valid in SRQ
    375 event:0X247 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP36 : (Group 36 pm_mark3) Instructions completed
    376 
    377 #Group 37 pm_lsu_mark1, Load Store Unit Marked Events
    378 event:0X250 counters:0 um:zero minimum:1000 name:PM_MRK_ST_MISS_L1_GRP37 : (Group 37 pm_lsu_mark1) Marked L1 D cache store misses
    379 event:0X251 counters:1 um:zero minimum:1000 name:PM_MRK_IMR_RELOAD_GRP37 : (Group 37 pm_lsu_mark1) Marked IMR reloaded
    380 event:0X252 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_UST_GRP37 : (Group 37 pm_lsu_mark1) LSU0 marked unaligned store flushes
    381 event:0X253 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_UST_GRP37 : (Group 37 pm_lsu_mark1) LSU1 marked unaligned store flushes
    382 event:0X254 counters:4 um:zero minimum:10000 name:PM_CYC_GRP37 : (Group 37 pm_lsu_mark1) Processor cycles
    383 event:0X255 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP37 : (Group 37 pm_lsu_mark1) Instructions completed
    384 event:0X256 counters:6 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_ULD_GRP37 : (Group 37 pm_lsu_mark1) LSU0 marked unaligned load flushes
    385 event:0X257 counters:7 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_ULD_GRP37 : (Group 37 pm_lsu_mark1) LSU1 marked unaligned load flushes
    386 
    387 #Group 38 pm_lsu_mark2, Load Store Unit Marked Events
    388 event:0X260 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU0_GRP38 : (Group 38 pm_lsu_mark2) LSU0 L1 D cache load misses
    389 event:0X261 counters:1 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU1_GRP38 : (Group 38 pm_lsu_mark2) LSU1 L1 D cache load misses
    390 event:0X262 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_LRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU0 marked LRQ flushes
    391 event:0X263 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_LRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU1 marked LRQ flushes
    392 event:0X264 counters:4 um:zero minimum:10000 name:PM_CYC_GRP38 : (Group 38 pm_lsu_mark2) Processor cycles
    393 event:0X265 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP38 : (Group 38 pm_lsu_mark2) Instructions completed
    394 event:0X266 counters:6 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_SRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU0 marked SRQ flushes
    395 event:0X267 counters:7 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_SRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU1 marked SRQ flushes
    396 
    397 #Group 39 pm_fxu1, Fixed Point events by unit
    398 event:0X270 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP39 : (Group 39 pm_fxu1) Instructions completed
    399 event:0X271 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP39 : (Group 39 pm_fxu1) Instructions completed
    400 event:0X272 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP39 : (Group 39 pm_fxu1) FXU produced a result
    401 event:0X273 counters:3 um:zero minimum:1000 name:PM_FXU1_BUSY_FXU0_IDLE_GRP39 : (Group 39 pm_fxu1) FXU1 busy FXU0 idle
    402 event:0X274 counters:4 um:zero minimum:1000 name:PM_FXU_IDLE_GRP39 : (Group 39 pm_fxu1) FXU idle
    403 event:0X275 counters:5 um:zero minimum:1000 name:PM_FXU_BUSY_GRP39 : (Group 39 pm_fxu1) FXU busy
    404 event:0X276 counters:6 um:zero minimum:1000 name:PM_FXU0_BUSY_FXU1_IDLE_GRP39 : (Group 39 pm_fxu1) FXU0 busy FXU1 idle
    405 event:0X277 counters:7 um:zero minimum:10000 name:PM_CYC_GRP39 : (Group 39 pm_fxu1) Processor cycles
    406 
    407 #Group 40 pm_fxu2, Fixed Point events by unit
    408 event:0X280 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP40 : (Group 40 pm_fxu2) Instructions completed
    409 event:0X281 counters:1 um:zero minimum:10000 name:PM_CYC_GRP40 : (Group 40 pm_fxu2) Processor cycles
    410 event:0X282 counters:2 um:zero minimum:1000 name:PM_FXLS1_FULL_CYC_GRP40 : (Group 40 pm_fxu2) Cycles FXU1/LS1 queue full
    411 event:0X283 counters:3 um:zero minimum:1000 name:PM_FXLS0_FULL_CYC_GRP40 : (Group 40 pm_fxu2) Cycles FXU0/LS0 queue full
    412 event:0X284 counters:4 um:zero minimum:1000 name:PM_FXU_IDLE_GRP40 : (Group 40 pm_fxu2) FXU idle
    413 event:0X285 counters:5 um:zero minimum:1000 name:PM_FXU_BUSY_GRP40 : (Group 40 pm_fxu2) FXU busy
    414 event:0X286 counters:6 um:zero minimum:1000 name:PM_FXU0_FIN_GRP40 : (Group 40 pm_fxu2) FXU0 produced a result
    415 event:0X287 counters:7 um:zero minimum:1000 name:PM_FXU1_FIN_GRP40 : (Group 40 pm_fxu2) FXU1 produced a result
    416 
    417 #Group 41 pm_ifu, pm_ifu
    418 event:0X290 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP41 : (Group 41 pm_ifu) Instruction fetched from L1
    419 event:0X291 counters:1 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP41 : (Group 41 pm_ifu) Instruction fetched from memory
    420 event:0X292 counters:2 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP41 : (Group 41 pm_ifu) Instructions fetched from prefetch
    421 event:0X293 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP41 : (Group 41 pm_ifu) No instructions fetched
    422 event:0X294 counters:4 um:zero minimum:1000 name:PM_INST_FETCH_CYC_GRP41 : (Group 41 pm_ifu) Cycles at least 1 instruction fetched
    423 event:0X295 counters:5 um:zero minimum:1000 name:PM_INST_FROM_L25_MOD_GRP41 : (Group 41 pm_ifu) Instruction fetched from L2.5 modified
    424 event:0X296 counters:6 um:zero minimum:10000 name:PM_CYC_GRP41 : (Group 41 pm_ifu) Processor cycles
    425 event:0X297 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP41 : (Group 41 pm_ifu) Instructions completed
    426 
    427 #Group 42 pm_cpi_stack1, CPI stack analysis
    428 event:0X2A0 counters:0 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP42 : (Group 42 pm_cpi_stack1) LSU0 busy
    429 event:0X2A1 counters:1 um:zero minimum:1000 name:PM_LSU1_BUSY_GRP42 : (Group 42 pm_cpi_stack1) LSU1 busy
    430 event:0X2A2 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP42 : (Group 42 pm_cpi_stack1) Flush initiated by LSU
    431 event:0X2A3 counters:3 um:zero minimum:1000 name:PM_FLUSH_LSU_BR_MPRED_GRP42 : (Group 42 pm_cpi_stack1) Flush caused by LSU or branch mispredict
    432 event:0X2A4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_LSU_GRP42 : (Group 42 pm_cpi_stack1) Completion stall caused by LSU instruction
    433 event:0X2A5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP42 : (Group 42 pm_cpi_stack1) Instructions completed
    434 event:0X2A6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_ERAT_MISS_GRP42 : (Group 42 pm_cpi_stack1) Completion stall caused by ERAT miss
    435 event:0X2A7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP42 : (Group 42 pm_cpi_stack1) Processor cycles
    436 
    437 #Group 43 pm_cpi_stack2, CPI stack analysis
    438 event:0X2B0 counters:0 um:zero minimum:1000 name:PM_CMPLU_STALL_OTHER_GRP43 : (Group 43 pm_cpi_stack2) Completion stall caused by other reason
    439 event:0X2B1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP43 : (Group 43 pm_cpi_stack2) Instructions completed
    440 event:0X2B2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP43 : (Group 43 pm_cpi_stack2) L1 D cache load misses
    441 event:0X2B3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP43 : (Group 43 pm_cpi_stack2) Processor cycles
    442 event:0X2B4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_DCACHE_MISS_GRP43 : (Group 43 pm_cpi_stack2) Completion stall caused by D cache miss
    443 event:0X2B5 counters:5 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP43 : (Group 43 pm_cpi_stack2) DERAT misses
    444 event:0X2B6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_REJECT_GRP43 : (Group 43 pm_cpi_stack2) Completion stall caused by reject
    445 event:0X2B7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP43 : (Group 43 pm_cpi_stack2) L1 D cache load references
    446 
    447 #Group 44 pm_cpi_stack3, CPI stack analysis
    448 event:0X2C0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP44 : (Group 44 pm_cpi_stack3) Instructions completed
    449 event:0X2C1 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_SRQ_FULL_GRP44 : (Group 44 pm_cpi_stack3) GCT empty caused by SRQ full
    450 event:0X2C2 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP44 : (Group 44 pm_cpi_stack3) FXU produced a result
    451 event:0X2C3 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP44 : (Group 44 pm_cpi_stack3) FPU produced a result
    452 event:0X2C4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_FXU_GRP44 : (Group 44 pm_cpi_stack3) Completion stall caused by FXU instruction
    453 event:0X2C5 counters:5 um:zero minimum:1000 name:PM_FXU_BUSY_GRP44 : (Group 44 pm_cpi_stack3) FXU busy
    454 event:0X2C6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_DIV_GRP44 : (Group 44 pm_cpi_stack3) Completion stall caused by DIV instruction
    455 event:0X2C7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP44 : (Group 44 pm_cpi_stack3) Processor cycles
    456 
    457 #Group 45 pm_cpi_stack4, CPI stack analysis
    458 event:0X2D0 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP45 : (Group 45 pm_cpi_stack4) FPU executed FDIV instruction
    459 event:0X2D1 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP45 : (Group 45 pm_cpi_stack4) FPU executed multiply-add instruction
    460 event:0X2D2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP45 : (Group 45 pm_cpi_stack4) Instructions completed
    461 event:0X2D3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP45 : (Group 45 pm_cpi_stack4) Instructions completed
    462 event:0X2D4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_FDIV_GRP45 : (Group 45 pm_cpi_stack4) Completion stall caused by FDIV or FQRT instruction
    463 event:0X2D5 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP45 : (Group 45 pm_cpi_stack4) FPU executed FSQRT instruction
    464 event:0X2D6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_FPU_GRP45 : (Group 45 pm_cpi_stack4) Completion stall caused by FPU instruction
    465 event:0X2D7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP45 : (Group 45 pm_cpi_stack4) Processor cycles
    466 
    467 #Group 46 pm_cpi_stack5, CPI stack analysis
    468 event:0X2E0 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP46 : (Group 46 pm_cpi_stack5) Cycles GCT empty
    469 event:0X2E1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP46 : (Group 46 pm_cpi_stack5) Instructions completed
    470 event:0X2E2 counters:2 um:zero minimum:1000 name:PM_FLUSH_BR_MPRED_GRP46 : (Group 46 pm_cpi_stack5) Flush caused by branch mispredict
    471 event:0X2E3 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP46 : (Group 46 pm_cpi_stack5) Branch mispredictions due to target address
    472 event:0X2E4 counters:4 um:zero minimum:1000 name:PM_GCT_EMPTY_IC_MISS_GRP46 : (Group 46 pm_cpi_stack5) GCT empty due to I cache miss
    473 event:0X2E5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP46 : (Group 46 pm_cpi_stack5) Processor cycles
    474 event:0X2E6 counters:6 um:zero minimum:1000 name:PM_GCT_EMPTY_BR_MPRED_GRP46 : (Group 46 pm_cpi_stack5) GCT empty due to branch mispredict
    475 event:0X2E7 counters:7 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP46 : (Group 46 pm_cpi_stack5) Cycles writing to instruction L1
    476 
    477 #Group 47 pm_data2, data source and LMQ
    478 event:0X2F0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP47 : (Group 47 pm_data2) Data loaded from L2.5 shared
    479 event:0X2F1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP47 : (Group 47 pm_data2) Instructions completed
    480 event:0X2F2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP47 : (Group 47 pm_data2) Data loaded from L2.5 modified
    481 event:0X2F3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP47 : (Group 47 pm_data2) Processor cycles
    482 event:0X2F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP47 : (Group 47 pm_data2) Instructions completed
    483 event:0X2F5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP47 : (Group 47 pm_data2) Processor cycles
    484 event:0X2F6 counters:6 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP47 : (Group 47 pm_data2) LMQ slot 0 allocated
    485 event:0X2F7 counters:7 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP47 : (Group 47 pm_data2) LMQ slot 0 valid
    486 
    487 #Group 48 pm_fetch_branch, Instruction fetch and branch events
    488 event:0X300 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP48 : (Group 48 pm_fetch_branch) Instructions fetched from L2
    489 event:0X301 counters:1 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP48 : (Group 48 pm_fetch_branch) Instruction fetched from memory
    490 event:0X302 counters:2 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP48 : (Group 48 pm_fetch_branch) Instructions fetched from prefetch
    491 event:0X303 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP48 : (Group 48 pm_fetch_branch) Branches issued
    492 event:0X304 counters:4 um:zero minimum:10000 name:PM_CYC_GRP48 : (Group 48 pm_fetch_branch) Processor cycles
    493 event:0X305 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP48 : (Group 48 pm_fetch_branch) Instructions completed
    494 event:0X306 counters:6 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP48 : (Group 48 pm_fetch_branch) Branch mispredictions due to CR bit setting
    495 event:0X307 counters:7 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP48 : (Group 48 pm_fetch_branch) Branch mispredictions due to target address
    496 
    497 #Group 49 pm_l1l2_miss, L1 and L2 miss events
    498 event:0X310 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP49 : (Group 49 pm_l1l2_miss) Data loaded from L2
    499 event:0X311 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP49 : (Group 49 pm_l1l2_miss) Instructions completed
    500 event:0X312 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP49 : (Group 49 pm_l1l2_miss) Data loaded from memory
    501 event:0X313 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP49 : (Group 49 pm_l1l2_miss) LSU0 L1 D cache load misses
    502 event:0X314 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP49 : (Group 49 pm_l1l2_miss) One or more PPC instruction completed
    503 event:0X315 counters:5 um:zero minimum:10000 name:PM_CYC_GRP49 : (Group 49 pm_l1l2_miss) Processor cycles
    504 event:0X316 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP49 : (Group 49 pm_l1l2_miss) LSU1 L1 D cache load misses
    505 event:0X317 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP49 : (Group 49 pm_l1l2_miss) L1 D cache load references
    506