1 /* Print mips instructions for GDB, the GNU debugger, or for objdump. 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003 4 Free Software Foundation, Inc. 5 Contributed by Nobuyuki Hikichi(hikichi (at) sra.co.jp). 6 7 This file is part of GDB, GAS, and the GNU binutils. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "dis-asm.h" 23 24 /* mips.h. Mips opcode list for GDB, the GNU debugger. 25 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 26 Free Software Foundation, Inc. 27 Contributed by Ralph Campbell and OSF 28 Commented and modified by Ian Lance Taylor, Cygnus Support 29 30 This file is part of GDB, GAS, and the GNU binutils. 31 32 GDB, GAS, and the GNU binutils are free software; you can redistribute 33 them and/or modify them under the terms of the GNU General Public 34 License as published by the Free Software Foundation; either version 35 1, or (at your option) any later version. 36 37 GDB, GAS, and the GNU binutils are distributed in the hope that they 38 will be useful, but WITHOUT ANY WARRANTY; without even the implied 39 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 40 the GNU General Public License for more details. 41 42 You should have received a copy of the GNU General Public License 43 along with this file; see the file COPYING. If not, 44 see <http://www.gnu.org/licenses/>. */ 45 46 /* These are bit masks and shift counts to use to access the various 47 fields of an instruction. To retrieve the X field of an 48 instruction, use the expression 49 (i >> OP_SH_X) & OP_MASK_X 50 To set the same field (to j), use 51 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 52 53 Make sure you use fields that are appropriate for the instruction, 54 of course. 55 56 The 'i' format uses OP, RS, RT and IMMEDIATE. 57 58 The 'j' format uses OP and TARGET. 59 60 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 61 62 The 'b' format uses OP, RS, RT and DELTA. 63 64 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 65 66 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 67 68 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 69 breakpoint instruction are not defined; Kane says the breakpoint 70 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 71 only use ten bits). An optional two-operand form of break/sdbbp 72 allows the lower ten bits to be set too, and MIPS32 and later 73 architectures allow 20 bits to be set with a signal operand 74 (using CODE20). 75 76 The syscall instruction uses CODE20. 77 78 The general coprocessor instructions use COPZ. */ 79 80 #define OP_MASK_OP 0x3f 81 #define OP_SH_OP 26 82 #define OP_MASK_RS 0x1f 83 #define OP_SH_RS 21 84 #define OP_MASK_FR 0x1f 85 #define OP_SH_FR 21 86 #define OP_MASK_FMT 0x1f 87 #define OP_SH_FMT 21 88 #define OP_MASK_BCC 0x7 89 #define OP_SH_BCC 18 90 #define OP_MASK_CODE 0x3ff 91 #define OP_SH_CODE 16 92 #define OP_MASK_CODE2 0x3ff 93 #define OP_SH_CODE2 6 94 #define OP_MASK_RT 0x1f 95 #define OP_SH_RT 16 96 #define OP_MASK_FT 0x1f 97 #define OP_SH_FT 16 98 #define OP_MASK_CACHE 0x1f 99 #define OP_SH_CACHE 16 100 #define OP_MASK_RD 0x1f 101 #define OP_SH_RD 11 102 #define OP_MASK_FS 0x1f 103 #define OP_SH_FS 11 104 #define OP_MASK_PREFX 0x1f 105 #define OP_SH_PREFX 11 106 #define OP_MASK_CCC 0x7 107 #define OP_SH_CCC 8 108 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 109 #define OP_SH_CODE20 6 110 #define OP_MASK_SHAMT 0x1f 111 #define OP_SH_SHAMT 6 112 #define OP_MASK_FD 0x1f 113 #define OP_SH_FD 6 114 #define OP_MASK_TARGET 0x3ffffff 115 #define OP_SH_TARGET 0 116 #define OP_MASK_COPZ 0x1ffffff 117 #define OP_SH_COPZ 0 118 #define OP_MASK_IMMEDIATE 0xffff 119 #define OP_SH_IMMEDIATE 0 120 #define OP_MASK_DELTA 0xffff 121 #define OP_SH_DELTA 0 122 #define OP_MASK_FUNCT 0x3f 123 #define OP_SH_FUNCT 0 124 #define OP_MASK_SPEC 0x3f 125 #define OP_SH_SPEC 0 126 #define OP_SH_LOCC 8 /* FP condition code. */ 127 #define OP_SH_HICC 18 /* FP condition code. */ 128 #define OP_MASK_CC 0x7 129 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 130 #define OP_MASK_COP1NORM 0x1 /* a single bit. */ 131 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 132 #define OP_MASK_COP1SPEC 0xf 133 #define OP_MASK_COP1SCLR 0x4 134 #define OP_MASK_COP1CMP 0x3 135 #define OP_SH_COP1CMP 4 136 #define OP_SH_FORMAT 21 /* FP short format field. */ 137 #define OP_MASK_FORMAT 0x7 138 #define OP_SH_TRUE 16 139 #define OP_MASK_TRUE 0x1 140 #define OP_SH_GE 17 141 #define OP_MASK_GE 0x01 142 #define OP_SH_UNSIGNED 16 143 #define OP_MASK_UNSIGNED 0x1 144 #define OP_SH_HINT 16 145 #define OP_MASK_HINT 0x1f 146 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 147 #define OP_MASK_MMI 0x3f 148 #define OP_SH_MMISUB 6 149 #define OP_MASK_MMISUB 0x1f 150 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 151 #define OP_SH_PERFREG 1 152 #define OP_SH_SEL 0 /* Coprocessor select field. */ 153 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 154 #define OP_SH_CODE19 6 /* 19 bit wait code. */ 155 #define OP_MASK_CODE19 0x7ffff 156 #define OP_SH_ALN 21 157 #define OP_MASK_ALN 0x7 158 #define OP_SH_VSEL 21 159 #define OP_MASK_VSEL 0x1f 160 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 161 but 0x8-0xf don't select bytes. */ 162 #define OP_SH_VECBYTE 22 163 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 164 #define OP_SH_VECALIGN 21 165 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 166 #define OP_SH_INSMSB 11 167 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 168 #define OP_SH_EXTMSBD 11 169 170 #define OP_OP_COP0 0x10 171 #define OP_OP_COP1 0x11 172 #define OP_OP_COP2 0x12 173 #define OP_OP_COP3 0x13 174 #define OP_OP_LWC1 0x31 175 #define OP_OP_LWC2 0x32 176 #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 177 #define OP_OP_LDC1 0x35 178 #define OP_OP_LDC2 0x36 179 #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 180 #define OP_OP_SWC1 0x39 181 #define OP_OP_SWC2 0x3a 182 #define OP_OP_SWC3 0x3b 183 #define OP_OP_SDC1 0x3d 184 #define OP_OP_SDC2 0x3e 185 #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 186 187 /* MIPS DSP ASE */ 188 #define OP_SH_DSPACC 11 189 #define OP_MASK_DSPACC 0x3 190 #define OP_SH_DSPACC_S 21 191 #define OP_MASK_DSPACC_S 0x3 192 #define OP_SH_DSPSFT 20 193 #define OP_MASK_DSPSFT 0x3f 194 #define OP_SH_DSPSFT_7 19 195 #define OP_MASK_DSPSFT_7 0x7f 196 #define OP_SH_SA3 21 197 #define OP_MASK_SA3 0x7 198 #define OP_SH_SA4 21 199 #define OP_MASK_SA4 0xf 200 #define OP_SH_IMM8 16 201 #define OP_MASK_IMM8 0xff 202 #define OP_SH_IMM10 16 203 #define OP_MASK_IMM10 0x3ff 204 #define OP_SH_WRDSP 11 205 #define OP_MASK_WRDSP 0x3f 206 #define OP_SH_RDDSP 16 207 #define OP_MASK_RDDSP 0x3f 208 #define OP_SH_BP 11 209 #define OP_MASK_BP 0x3 210 211 /* MIPS MT ASE */ 212 #define OP_SH_MT_U 5 213 #define OP_MASK_MT_U 0x1 214 #define OP_SH_MT_H 4 215 #define OP_MASK_MT_H 0x1 216 #define OP_SH_MTACC_T 18 217 #define OP_MASK_MTACC_T 0x3 218 #define OP_SH_MTACC_D 13 219 #define OP_MASK_MTACC_D 0x3 220 221 #define OP_OP_COP0 0x10 222 #define OP_OP_COP1 0x11 223 #define OP_OP_COP2 0x12 224 #define OP_OP_COP3 0x13 225 #define OP_OP_LWC1 0x31 226 #define OP_OP_LWC2 0x32 227 #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 228 #define OP_OP_LDC1 0x35 229 #define OP_OP_LDC2 0x36 230 #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 231 #define OP_OP_SWC1 0x39 232 #define OP_OP_SWC2 0x3a 233 #define OP_OP_SWC3 0x3b 234 #define OP_OP_SDC1 0x3d 235 #define OP_OP_SDC2 0x3e 236 #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 237 238 /* Values in the 'VSEL' field. */ 239 #define MDMX_FMTSEL_IMM_QH 0x1d 240 #define MDMX_FMTSEL_IMM_OB 0x1e 241 #define MDMX_FMTSEL_VEC_QH 0x15 242 #define MDMX_FMTSEL_VEC_OB 0x16 243 244 /* UDI */ 245 #define OP_SH_UDI1 6 246 #define OP_MASK_UDI1 0x1f 247 #define OP_SH_UDI2 6 248 #define OP_MASK_UDI2 0x3ff 249 #define OP_SH_UDI3 6 250 #define OP_MASK_UDI3 0x7fff 251 #define OP_SH_UDI4 6 252 #define OP_MASK_UDI4 0xfffff 253 /* This structure holds information for a particular instruction. */ 254 255 struct mips_opcode 256 { 257 /* The name of the instruction. */ 258 const char *name; 259 /* A string describing the arguments for this instruction. */ 260 const char *args; 261 /* The basic opcode for the instruction. When assembling, this 262 opcode is modified by the arguments to produce the actual opcode 263 that is used. If pinfo is INSN_MACRO, then this is 0. */ 264 unsigned long match; 265 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 266 relevant portions of the opcode when disassembling. If the 267 actual opcode anded with the match field equals the opcode field, 268 then we have found the correct instruction. If pinfo is 269 INSN_MACRO, then this field is the macro identifier. */ 270 unsigned long mask; 271 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 272 of bits describing the instruction, notably any relevant hazard 273 information. */ 274 unsigned long pinfo; 275 /* A collection of additional bits describing the instruction. */ 276 unsigned long pinfo2; 277 /* A collection of bits describing the instruction sets of which this 278 instruction or macro is a member. */ 279 unsigned long membership; 280 }; 281 282 /* These are the characters which may appear in the args field of an 283 instruction. They appear in the order in which the fields appear 284 when the instruction is used. Commas and parentheses in the args 285 string are ignored when assembling, and written into the output 286 when disassembling. 287 288 Each of these characters corresponds to a mask field defined above. 289 290 "<" 5 bit shift amount (OP_*_SHAMT) 291 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 292 "a" 26 bit target address (OP_*_TARGET) 293 "b" 5 bit base register (OP_*_RS) 294 "c" 10 bit breakpoint code (OP_*_CODE) 295 "d" 5 bit destination register specifier (OP_*_RD) 296 "h" 5 bit prefx hint (OP_*_PREFX) 297 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 298 "j" 16 bit signed immediate (OP_*_DELTA) 299 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 300 Also used for immediate operands in vr5400 vector insns. 301 "o" 16 bit signed offset (OP_*_DELTA) 302 "p" 16 bit PC relative branch target address (OP_*_DELTA) 303 "q" 10 bit extra breakpoint code (OP_*_CODE2) 304 "r" 5 bit same register used as both source and target (OP_*_RS) 305 "s" 5 bit source register specifier (OP_*_RS) 306 "t" 5 bit target register (OP_*_RT) 307 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 308 "v" 5 bit same register used as both source and destination (OP_*_RS) 309 "w" 5 bit same register used as both target and destination (OP_*_RT) 310 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 311 (used by clo and clz) 312 "C" 25 bit coprocessor function code (OP_*_COPZ) 313 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 314 "J" 19 bit wait function code (OP_*_CODE19) 315 "x" accept and ignore register name 316 "z" must be zero register 317 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 318 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes 319 LSB (OP_*_SHAMT). 320 Enforces: 0 <= pos < 32. 321 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). 322 Requires that "+A" or "+E" occur first to set position. 323 Enforces: 0 < (pos+size) <= 32. 324 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). 325 Requires that "+A" or "+E" occur first to set position. 326 Enforces: 0 < (pos+size) <= 32. 327 (Also used by "dext" w/ different limits, but limits for 328 that are checked by the M_DEXT macro.) 329 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). 330 Enforces: 32 <= pos < 64. 331 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). 332 Requires that "+A" or "+E" occur first to set position. 333 Enforces: 32 < (pos+size) <= 64. 334 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 335 Requires that "+A" or "+E" occur first to set position. 336 Enforces: 32 < (pos+size) <= 64. 337 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 338 Requires that "+A" or "+E" occur first to set position. 339 Enforces: 32 < (pos+size) <= 64. 340 341 Floating point instructions: 342 "D" 5 bit destination register (OP_*_FD) 343 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 344 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 345 "S" 5 bit fs source 1 register (OP_*_FS) 346 "T" 5 bit ft source 2 register (OP_*_FT) 347 "R" 5 bit fr source 3 register (OP_*_FR) 348 "V" 5 bit same register used as floating source and destination (OP_*_FS) 349 "W" 5 bit same register used as floating target and destination (OP_*_FT) 350 351 Coprocessor instructions: 352 "E" 5 bit target register (OP_*_RT) 353 "G" 5 bit destination register (OP_*_RD) 354 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 355 "P" 5 bit performance-monitor register (OP_*_PERFREG) 356 "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 357 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 358 see also "k" above 359 "+D" Combined destination register ("G") and sel ("H") for CP0 ops, 360 for pretty-printing in disassembly only. 361 362 Macro instructions: 363 "A" General 32 bit expression 364 "I" 32 bit immediate (value placed in imm_expr). 365 "+I" 32 bit immediate (value placed in imm2_expr). 366 "F" 64 bit floating point constant in .rdata 367 "L" 64 bit floating point constant in .lit8 368 "f" 32 bit floating point constant 369 "l" 32 bit floating point constant in .lit4 370 371 MDMX instruction operands (note that while these use the FP register 372 fields, they accept both $fN and $vN names for the registers): 373 "O" MDMX alignment offset (OP_*_ALN) 374 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 375 "X" MDMX destination register (OP_*_FD) 376 "Y" MDMX source register (OP_*_FS) 377 "Z" MDMX source register (OP_*_FT) 378 379 DSP ASE usage: 380 "2" 2 bit unsigned immediate for byte align (OP_*_BP) 381 "3" 3 bit unsigned immediate (OP_*_SA3) 382 "4" 4 bit unsigned immediate (OP_*_SA4) 383 "5" 8 bit unsigned immediate (OP_*_IMM8) 384 "6" 5 bit unsigned immediate (OP_*_RS) 385 "7" 2 bit dsp accumulator register (OP_*_DSPACC) 386 "8" 6 bit unsigned immediate (OP_*_WRDSP) 387 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) 388 "0" 6 bit signed immediate (OP_*_DSPSFT) 389 ":" 7 bit signed immediate (OP_*_DSPSFT_7) 390 "'" 6 bit unsigned immediate (OP_*_RDDSP) 391 "@" 10 bit signed immediate (OP_*_IMM10) 392 393 MT ASE usage: 394 "!" 1 bit usermode flag (OP_*_MT_U) 395 "$" 1 bit load high flag (OP_*_MT_H) 396 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) 397 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) 398 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) 399 "+t" 5 bit coprocessor 0 destination register (OP_*_RT) 400 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only 401 402 UDI immediates: 403 "+1" UDI immediate bits 6-10 404 "+2" UDI immediate bits 6-15 405 "+3" UDI immediate bits 6-20 406 "+4" UDI immediate bits 6-25 407 408 Other: 409 "()" parens surrounding optional value 410 "," separates operands 411 "[]" brackets around index for vector-op scalar operand specifier (vr5400) 412 "+" Start of extension sequence. 413 414 Characters used so far, for quick reference when adding more: 415 "234567890" 416 "%[]<>(),+:'@!$*&" 417 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 418 "abcdefghijklopqrstuvwxz" 419 420 Extension character sequences used so far ("+" followed by the 421 following), for quick reference when adding more: 422 "1234" 423 "ABCDEFGHIT" 424 "t" 425 */ 426 427 /* These are the bits which may be set in the pinfo field of an 428 instructions, if it is not equal to INSN_MACRO. */ 429 430 /* Modifies the general purpose register in OP_*_RD. */ 431 #define INSN_WRITE_GPR_D 0x00000001 432 /* Modifies the general purpose register in OP_*_RT. */ 433 #define INSN_WRITE_GPR_T 0x00000002 434 /* Modifies general purpose register 31. */ 435 #define INSN_WRITE_GPR_31 0x00000004 436 /* Modifies the floating point register in OP_*_FD. */ 437 #define INSN_WRITE_FPR_D 0x00000008 438 /* Modifies the floating point register in OP_*_FS. */ 439 #define INSN_WRITE_FPR_S 0x00000010 440 /* Modifies the floating point register in OP_*_FT. */ 441 #define INSN_WRITE_FPR_T 0x00000020 442 /* Reads the general purpose register in OP_*_RS. */ 443 #define INSN_READ_GPR_S 0x00000040 444 /* Reads the general purpose register in OP_*_RT. */ 445 #define INSN_READ_GPR_T 0x00000080 446 /* Reads the floating point register in OP_*_FS. */ 447 #define INSN_READ_FPR_S 0x00000100 448 /* Reads the floating point register in OP_*_FT. */ 449 #define INSN_READ_FPR_T 0x00000200 450 /* Reads the floating point register in OP_*_FR. */ 451 #define INSN_READ_FPR_R 0x00000400 452 /* Modifies coprocessor condition code. */ 453 #define INSN_WRITE_COND_CODE 0x00000800 454 /* Reads coprocessor condition code. */ 455 #define INSN_READ_COND_CODE 0x00001000 456 /* TLB operation. */ 457 #define INSN_TLB 0x00002000 458 /* Reads coprocessor register other than floating point register. */ 459 #define INSN_COP 0x00004000 460 /* Instruction loads value from memory, requiring delay. */ 461 #define INSN_LOAD_MEMORY_DELAY 0x00008000 462 /* Instruction loads value from coprocessor, requiring delay. */ 463 #define INSN_LOAD_COPROC_DELAY 0x00010000 464 /* Instruction has unconditional branch delay slot. */ 465 #define INSN_UNCOND_BRANCH_DELAY 0x00020000 466 /* Instruction has conditional branch delay slot. */ 467 #define INSN_COND_BRANCH_DELAY 0x00040000 468 /* Conditional branch likely: if branch not taken, insn nullified. */ 469 #define INSN_COND_BRANCH_LIKELY 0x00080000 470 /* Moves to coprocessor register, requiring delay. */ 471 #define INSN_COPROC_MOVE_DELAY 0x00100000 472 /* Loads coprocessor register from memory, requiring delay. */ 473 #define INSN_COPROC_MEMORY_DELAY 0x00200000 474 /* Reads the HI register. */ 475 #define INSN_READ_HI 0x00400000 476 /* Reads the LO register. */ 477 #define INSN_READ_LO 0x00800000 478 /* Modifies the HI register. */ 479 #define INSN_WRITE_HI 0x01000000 480 /* Modifies the LO register. */ 481 #define INSN_WRITE_LO 0x02000000 482 /* Takes a trap (easier to keep out of delay slot). */ 483 #define INSN_TRAP 0x04000000 484 /* Instruction stores value into memory. */ 485 #define INSN_STORE_MEMORY 0x08000000 486 /* Instruction uses single precision floating point. */ 487 #define FP_S 0x10000000 488 /* Instruction uses double precision floating point. */ 489 #define FP_D 0x20000000 490 /* Instruction is part of the tx39's integer multiply family. */ 491 #define INSN_MULT 0x40000000 492 /* Instruction synchronize shared memory. */ 493 #define INSN_SYNC 0x80000000 494 495 /* These are the bits which may be set in the pinfo2 field of an 496 instruction. */ 497 498 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 499 #define INSN2_ALIAS 0x00000001 500 /* Instruction reads MDMX accumulator. */ 501 #define INSN2_READ_MDMX_ACC 0x00000002 502 /* Instruction writes MDMX accumulator. */ 503 #define INSN2_WRITE_MDMX_ACC 0x00000004 504 505 /* Instruction is actually a macro. It should be ignored by the 506 disassembler, and requires special treatment by the assembler. */ 507 #define INSN_MACRO 0xffffffff 508 509 /* Masks used to mark instructions to indicate which MIPS ISA level 510 they were introduced in. ISAs, as defined below, are logical 511 ORs of these bits, indicating that they support the instructions 512 defined at the given level. */ 513 514 #define INSN_ISA_MASK 0x00000fff 515 #define INSN_ISA1 0x00000001 516 #define INSN_ISA2 0x00000002 517 #define INSN_ISA3 0x00000004 518 #define INSN_ISA4 0x00000008 519 #define INSN_ISA5 0x00000010 520 #define INSN_ISA32 0x00000020 521 #define INSN_ISA64 0x00000040 522 #define INSN_ISA32R2 0x00000080 523 #define INSN_ISA64R2 0x00000100 524 525 /* Masks used for MIPS-defined ASEs. */ 526 #define INSN_ASE_MASK 0x0000f000 527 528 /* DSP ASE */ 529 #define INSN_DSP 0x00001000 530 #define INSN_DSP64 0x00002000 531 /* MIPS 16 ASE */ 532 #define INSN_MIPS16 0x00004000 533 /* MIPS-3D ASE */ 534 #define INSN_MIPS3D 0x00008000 535 536 /* Chip specific instructions. These are bitmasks. */ 537 538 /* MIPS R4650 instruction. */ 539 #define INSN_4650 0x00010000 540 /* LSI R4010 instruction. */ 541 #define INSN_4010 0x00020000 542 /* NEC VR4100 instruction. */ 543 #define INSN_4100 0x00040000 544 /* Toshiba R3900 instruction. */ 545 #define INSN_3900 0x00080000 546 /* MIPS R10000 instruction. */ 547 #define INSN_10000 0x00100000 548 /* Broadcom SB-1 instruction. */ 549 #define INSN_SB1 0x00200000 550 /* NEC VR4111/VR4181 instruction. */ 551 #define INSN_4111 0x00400000 552 /* NEC VR4120 instruction. */ 553 #define INSN_4120 0x00800000 554 /* NEC VR5400 instruction. */ 555 #define INSN_5400 0x01000000 556 /* NEC VR5500 instruction. */ 557 #define INSN_5500 0x02000000 558 559 /* MDMX ASE */ 560 #define INSN_MDMX 0x04000000 561 /* MT ASE */ 562 #define INSN_MT 0x08000000 563 /* SmartMIPS ASE */ 564 #define INSN_SMARTMIPS 0x10000000 565 /* DSP R2 ASE */ 566 #define INSN_DSPR2 0x20000000 567 568 /* MIPS ISA defines, use instead of hardcoding ISA level. */ 569 570 #define ISA_UNKNOWN 0 /* Gas internal use. */ 571 #define ISA_MIPS1 (INSN_ISA1) 572 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) 573 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) 574 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) 575 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) 576 577 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) 578 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) 579 580 #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) 581 #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) 582 583 584 /* CPU defines, use instead of hardcoding processor number. Keep this 585 in sync with bfd/archures.c in order for machine selection to work. */ 586 #define CPU_UNKNOWN 0 /* Gas internal use. */ 587 #define CPU_R3000 3000 588 #define CPU_R3900 3900 589 #define CPU_R4000 4000 590 #define CPU_R4010 4010 591 #define CPU_VR4100 4100 592 #define CPU_R4111 4111 593 #define CPU_VR4120 4120 594 #define CPU_R4300 4300 595 #define CPU_R4400 4400 596 #define CPU_R4600 4600 597 #define CPU_R4650 4650 598 #define CPU_R5000 5000 599 #define CPU_VR5400 5400 600 #define CPU_VR5500 5500 601 #define CPU_R6000 6000 602 #define CPU_RM7000 7000 603 #define CPU_R8000 8000 604 #define CPU_R10000 10000 605 #define CPU_R12000 12000 606 #define CPU_MIPS16 16 607 #define CPU_MIPS32 32 608 #define CPU_MIPS32R2 33 609 #define CPU_MIPS5 5 610 #define CPU_MIPS64 64 611 #define CPU_MIPS64R2 65 612 #define CPU_SB1 12310201 /* octal 'SB', 01. */ 613 614 /* Test for membership in an ISA including chip specific ISAs. INSN 615 is pointer to an element of the opcode table; ISA is the specified 616 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to 617 test, or zero if no CPU specific ISA test is desired. */ 618 619 #if 0 620 #define OPCODE_IS_MEMBER(insn, isa, cpu) \ 621 (((insn)->membership & isa) != 0 \ 622 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ 623 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ 624 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ 625 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ 626 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ 627 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ 628 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ 629 && ((insn)->membership & INSN_10000) != 0) \ 630 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ 631 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ 632 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ 633 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ 634 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ 635 || 0) /* Please keep this term for easier source merging. */ 636 #else 637 #define OPCODE_IS_MEMBER(insn, isa, cpu) \ 638 (1 != 0) 639 #endif 640 641 /* This is a list of macro expanded instructions. 642 643 _I appended means immediate 644 _A appended means address 645 _AB appended means address with base register 646 _D appended means 64 bit floating point constant 647 _S appended means 32 bit floating point constant. */ 648 649 enum 650 { 651 M_ABS, 652 M_ADD_I, 653 M_ADDU_I, 654 M_AND_I, 655 M_BALIGN, 656 M_BEQ, 657 M_BEQ_I, 658 M_BEQL_I, 659 M_BGE, 660 M_BGEL, 661 M_BGE_I, 662 M_BGEL_I, 663 M_BGEU, 664 M_BGEUL, 665 M_BGEU_I, 666 M_BGEUL_I, 667 M_BGT, 668 M_BGTL, 669 M_BGT_I, 670 M_BGTL_I, 671 M_BGTU, 672 M_BGTUL, 673 M_BGTU_I, 674 M_BGTUL_I, 675 M_BLE, 676 M_BLEL, 677 M_BLE_I, 678 M_BLEL_I, 679 M_BLEU, 680 M_BLEUL, 681 M_BLEU_I, 682 M_BLEUL_I, 683 M_BLT, 684 M_BLTL, 685 M_BLT_I, 686 M_BLTL_I, 687 M_BLTU, 688 M_BLTUL, 689 M_BLTU_I, 690 M_BLTUL_I, 691 M_BNE, 692 M_BNE_I, 693 M_BNEL_I, 694 M_CACHE_AB, 695 M_DABS, 696 M_DADD_I, 697 M_DADDU_I, 698 M_DDIV_3, 699 M_DDIV_3I, 700 M_DDIVU_3, 701 M_DDIVU_3I, 702 M_DEXT, 703 M_DINS, 704 M_DIV_3, 705 M_DIV_3I, 706 M_DIVU_3, 707 M_DIVU_3I, 708 M_DLA_AB, 709 M_DLCA_AB, 710 M_DLI, 711 M_DMUL, 712 M_DMUL_I, 713 M_DMULO, 714 M_DMULO_I, 715 M_DMULOU, 716 M_DMULOU_I, 717 M_DREM_3, 718 M_DREM_3I, 719 M_DREMU_3, 720 M_DREMU_3I, 721 M_DSUB_I, 722 M_DSUBU_I, 723 M_DSUBU_I_2, 724 M_J_A, 725 M_JAL_1, 726 M_JAL_2, 727 M_JAL_A, 728 M_L_DOB, 729 M_L_DAB, 730 M_LA_AB, 731 M_LB_A, 732 M_LB_AB, 733 M_LBU_A, 734 M_LBU_AB, 735 M_LCA_AB, 736 M_LD_A, 737 M_LD_OB, 738 M_LD_AB, 739 M_LDC1_AB, 740 M_LDC2_AB, 741 M_LDC3_AB, 742 M_LDL_AB, 743 M_LDR_AB, 744 M_LH_A, 745 M_LH_AB, 746 M_LHU_A, 747 M_LHU_AB, 748 M_LI, 749 M_LI_D, 750 M_LI_DD, 751 M_LI_S, 752 M_LI_SS, 753 M_LL_AB, 754 M_LLD_AB, 755 M_LS_A, 756 M_LW_A, 757 M_LW_AB, 758 M_LWC0_A, 759 M_LWC0_AB, 760 M_LWC1_A, 761 M_LWC1_AB, 762 M_LWC2_A, 763 M_LWC2_AB, 764 M_LWC3_A, 765 M_LWC3_AB, 766 M_LWL_A, 767 M_LWL_AB, 768 M_LWR_A, 769 M_LWR_AB, 770 M_LWU_AB, 771 M_MOVE, 772 M_MUL, 773 M_MUL_I, 774 M_MULO, 775 M_MULO_I, 776 M_MULOU, 777 M_MULOU_I, 778 M_NOR_I, 779 M_OR_I, 780 M_REM_3, 781 M_REM_3I, 782 M_REMU_3, 783 M_REMU_3I, 784 M_DROL, 785 M_ROL, 786 M_DROL_I, 787 M_ROL_I, 788 M_DROR, 789 M_ROR, 790 M_DROR_I, 791 M_ROR_I, 792 M_S_DA, 793 M_S_DOB, 794 M_S_DAB, 795 M_S_S, 796 M_SC_AB, 797 M_SCD_AB, 798 M_SD_A, 799 M_SD_OB, 800 M_SD_AB, 801 M_SDC1_AB, 802 M_SDC2_AB, 803 M_SDC3_AB, 804 M_SDL_AB, 805 M_SDR_AB, 806 M_SEQ, 807 M_SEQ_I, 808 M_SGE, 809 M_SGE_I, 810 M_SGEU, 811 M_SGEU_I, 812 M_SGT, 813 M_SGT_I, 814 M_SGTU, 815 M_SGTU_I, 816 M_SLE, 817 M_SLE_I, 818 M_SLEU, 819 M_SLEU_I, 820 M_SLT_I, 821 M_SLTU_I, 822 M_SNE, 823 M_SNE_I, 824 M_SB_A, 825 M_SB_AB, 826 M_SH_A, 827 M_SH_AB, 828 M_SW_A, 829 M_SW_AB, 830 M_SWC0_A, 831 M_SWC0_AB, 832 M_SWC1_A, 833 M_SWC1_AB, 834 M_SWC2_A, 835 M_SWC2_AB, 836 M_SWC3_A, 837 M_SWC3_AB, 838 M_SWL_A, 839 M_SWL_AB, 840 M_SWR_A, 841 M_SWR_AB, 842 M_SUB_I, 843 M_SUBU_I, 844 M_SUBU_I_2, 845 M_TEQ_I, 846 M_TGE_I, 847 M_TGEU_I, 848 M_TLT_I, 849 M_TLTU_I, 850 M_TNE_I, 851 M_TRUNCWD, 852 M_TRUNCWS, 853 M_ULD, 854 M_ULD_A, 855 M_ULH, 856 M_ULH_A, 857 M_ULHU, 858 M_ULHU_A, 859 M_ULW, 860 M_ULW_A, 861 M_USH, 862 M_USH_A, 863 M_USW, 864 M_USW_A, 865 M_USD, 866 M_USD_A, 867 M_XOR_I, 868 M_COP0, 869 M_COP1, 870 M_COP2, 871 M_COP3, 872 M_NUM_MACROS 873 }; 874 875 876 /* The order of overloaded instructions matters. Label arguments and 877 register arguments look the same. Instructions that can have either 878 for arguments must apear in the correct order in this table for the 879 assembler to pick the right one. In other words, entries with 880 immediate operands must apear after the same instruction with 881 registers. 882 883 Many instructions are short hand for other instructions (i.e., The 884 jal <register> instruction is short for jalr <register>). */ 885 886 extern const struct mips_opcode mips_builtin_opcodes[]; 887 extern const int bfd_mips_num_builtin_opcodes; 888 extern struct mips_opcode *mips_opcodes; 889 extern int bfd_mips_num_opcodes; 890 #define NUMOPCODES bfd_mips_num_opcodes 891 892 893 /* The rest of this file adds definitions for the mips16 TinyRISC 895 processor. */ 896 897 /* These are the bitmasks and shift counts used for the different 898 fields in the instruction formats. Other than OP, no masks are 899 provided for the fixed portions of an instruction, since they are 900 not needed. 901 902 The I format uses IMM11. 903 904 The RI format uses RX and IMM8. 905 906 The RR format uses RX, and RY. 907 908 The RRI format uses RX, RY, and IMM5. 909 910 The RRR format uses RX, RY, and RZ. 911 912 The RRI_A format uses RX, RY, and IMM4. 913 914 The SHIFT format uses RX, RY, and SHAMT. 915 916 The I8 format uses IMM8. 917 918 The I8_MOVR32 format uses RY and REGR32. 919 920 The IR_MOV32R format uses REG32R and MOV32Z. 921 922 The I64 format uses IMM8. 923 924 The RI64 format uses RY and IMM5. 925 */ 926 927 #define MIPS16OP_MASK_OP 0x1f 928 #define MIPS16OP_SH_OP 11 929 #define MIPS16OP_MASK_IMM11 0x7ff 930 #define MIPS16OP_SH_IMM11 0 931 #define MIPS16OP_MASK_RX 0x7 932 #define MIPS16OP_SH_RX 8 933 #define MIPS16OP_MASK_IMM8 0xff 934 #define MIPS16OP_SH_IMM8 0 935 #define MIPS16OP_MASK_RY 0x7 936 #define MIPS16OP_SH_RY 5 937 #define MIPS16OP_MASK_IMM5 0x1f 938 #define MIPS16OP_SH_IMM5 0 939 #define MIPS16OP_MASK_RZ 0x7 940 #define MIPS16OP_SH_RZ 2 941 #define MIPS16OP_MASK_IMM4 0xf 942 #define MIPS16OP_SH_IMM4 0 943 #define MIPS16OP_MASK_REGR32 0x1f 944 #define MIPS16OP_SH_REGR32 0 945 #define MIPS16OP_MASK_REG32R 0x1f 946 #define MIPS16OP_SH_REG32R 3 947 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 948 #define MIPS16OP_MASK_MOVE32Z 0x7 949 #define MIPS16OP_SH_MOVE32Z 0 950 #define MIPS16OP_MASK_IMM6 0x3f 951 #define MIPS16OP_SH_IMM6 5 952 953 /* These are the characters which may appears in the args field of an 954 instruction. They appear in the order in which the fields appear 955 when the instruction is used. Commas and parentheses in the args 956 string are ignored when assembling, and written into the output 957 when disassembling. 958 959 "y" 3 bit register (MIPS16OP_*_RY) 960 "x" 3 bit register (MIPS16OP_*_RX) 961 "z" 3 bit register (MIPS16OP_*_RZ) 962 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 963 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 964 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 965 "0" zero register ($0) 966 "S" stack pointer ($sp or $29) 967 "P" program counter 968 "R" return address register ($ra or $31) 969 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 970 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 971 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 972 "a" 26 bit jump address 973 "e" 11 bit extension value 974 "l" register list for entry instruction 975 "L" register list for exit instruction 976 977 The remaining codes may be extended. Except as otherwise noted, 978 the full extended operand is a 16 bit signed value. 979 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 980 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) 981 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 982 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 983 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 984 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 985 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 986 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 987 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 988 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 989 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 990 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 991 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 992 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 993 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 994 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 995 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 996 "q" 11 bit branch address (MIPS16OP_*_IMM11) 997 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 998 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 999 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 1000 */ 1001 1002 /* Save/restore encoding for the args field when all 4 registers are 1003 either saved as arguments or saved/restored as statics. */ 1004 #define MIPS16_ALL_ARGS 0xe 1005 #define MIPS16_ALL_STATICS 0xb 1006 1007 /* For the mips16, we use the same opcode table format and a few of 1008 the same flags. However, most of the flags are different. */ 1009 1010 /* Modifies the register in MIPS16OP_*_RX. */ 1011 #define MIPS16_INSN_WRITE_X 0x00000001 1012 /* Modifies the register in MIPS16OP_*_RY. */ 1013 #define MIPS16_INSN_WRITE_Y 0x00000002 1014 /* Modifies the register in MIPS16OP_*_RZ. */ 1015 #define MIPS16_INSN_WRITE_Z 0x00000004 1016 /* Modifies the T ($24) register. */ 1017 #define MIPS16_INSN_WRITE_T 0x00000008 1018 /* Modifies the SP ($29) register. */ 1019 #define MIPS16_INSN_WRITE_SP 0x00000010 1020 /* Modifies the RA ($31) register. */ 1021 #define MIPS16_INSN_WRITE_31 0x00000020 1022 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ 1023 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 1024 /* Reads the register in MIPS16OP_*_RX. */ 1025 #define MIPS16_INSN_READ_X 0x00000080 1026 /* Reads the register in MIPS16OP_*_RY. */ 1027 #define MIPS16_INSN_READ_Y 0x00000100 1028 /* Reads the register in MIPS16OP_*_MOVE32Z. */ 1029 #define MIPS16_INSN_READ_Z 0x00000200 1030 /* Reads the T ($24) register. */ 1031 #define MIPS16_INSN_READ_T 0x00000400 1032 /* Reads the SP ($29) register. */ 1033 #define MIPS16_INSN_READ_SP 0x00000800 1034 /* Reads the RA ($31) register. */ 1035 #define MIPS16_INSN_READ_31 0x00001000 1036 /* Reads the program counter. */ 1037 #define MIPS16_INSN_READ_PC 0x00002000 1038 /* Reads the general purpose register in MIPS16OP_*_REGR32. */ 1039 #define MIPS16_INSN_READ_GPR_X 0x00004000 1040 /* Is a branch insn. */ 1041 #define MIPS16_INSN_BRANCH 0x00010000 1042 1043 /* The following flags have the same value for the mips16 opcode 1044 table: 1045 INSN_UNCOND_BRANCH_DELAY 1046 INSN_COND_BRANCH_DELAY 1047 INSN_COND_BRANCH_LIKELY (never used) 1048 INSN_READ_HI 1049 INSN_READ_LO 1050 INSN_WRITE_HI 1051 INSN_WRITE_LO 1052 INSN_TRAP 1053 INSN_ISA3 1054 */ 1055 1056 extern const struct mips_opcode mips16_opcodes[]; 1057 extern const int bfd_mips16_num_opcodes; 1058 1059 /* Short hand so the lines aren't too long. */ 1060 1061 #define LDD INSN_LOAD_MEMORY_DELAY 1062 #define LCD INSN_LOAD_COPROC_DELAY 1063 #define UBD INSN_UNCOND_BRANCH_DELAY 1064 #define CBD INSN_COND_BRANCH_DELAY 1065 #define COD INSN_COPROC_MOVE_DELAY 1066 #define CLD INSN_COPROC_MEMORY_DELAY 1067 #define CBL INSN_COND_BRANCH_LIKELY 1068 #define TRAP INSN_TRAP 1069 #define SM INSN_STORE_MEMORY 1070 1071 #define WR_d INSN_WRITE_GPR_D 1072 #define WR_t INSN_WRITE_GPR_T 1073 #define WR_31 INSN_WRITE_GPR_31 1074 #define WR_D INSN_WRITE_FPR_D 1075 #define WR_T INSN_WRITE_FPR_T 1076 #define WR_S INSN_WRITE_FPR_S 1077 #define RD_s INSN_READ_GPR_S 1078 #define RD_b INSN_READ_GPR_S 1079 #define RD_t INSN_READ_GPR_T 1080 #define RD_S INSN_READ_FPR_S 1081 #define RD_T INSN_READ_FPR_T 1082 #define RD_R INSN_READ_FPR_R 1083 #define WR_CC INSN_WRITE_COND_CODE 1084 #define RD_CC INSN_READ_COND_CODE 1085 #define RD_C0 INSN_COP 1086 #define RD_C1 INSN_COP 1087 #define RD_C2 INSN_COP 1088 #define RD_C3 INSN_COP 1089 #define WR_C0 INSN_COP 1090 #define WR_C1 INSN_COP 1091 #define WR_C2 INSN_COP 1092 #define WR_C3 INSN_COP 1093 1094 #define WR_HI INSN_WRITE_HI 1095 #define RD_HI INSN_READ_HI 1096 #define MOD_HI WR_HI|RD_HI 1097 1098 #define WR_LO INSN_WRITE_LO 1099 #define RD_LO INSN_READ_LO 1100 #define MOD_LO WR_LO|RD_LO 1101 1102 #define WR_HILO WR_HI|WR_LO 1103 #define RD_HILO RD_HI|RD_LO 1104 #define MOD_HILO WR_HILO|RD_HILO 1105 1106 #define IS_M INSN_MULT 1107 1108 #define WR_MACC INSN2_WRITE_MDMX_ACC 1109 #define RD_MACC INSN2_READ_MDMX_ACC 1110 1111 #define I1 INSN_ISA1 1112 #define I2 INSN_ISA2 1113 #define I3 INSN_ISA3 1114 #define I4 INSN_ISA4 1115 #define I5 INSN_ISA5 1116 #define I32 INSN_ISA32 1117 #define I64 INSN_ISA64 1118 #define I33 INSN_ISA32R2 1119 #define I65 INSN_ISA64R2 1120 1121 /* MIPS64 MIPS-3D ASE support. */ 1122 #define I16 INSN_MIPS16 1123 1124 /* MIPS32 SmartMIPS ASE support. */ 1125 #define SMT INSN_SMARTMIPS 1126 1127 /* MIPS64 MIPS-3D ASE support. */ 1128 #define M3D INSN_MIPS3D 1129 1130 /* MIPS64 MDMX ASE support. */ 1131 #define MX INSN_MDMX 1132 1133 #define P3 INSN_4650 1134 #define L1 INSN_4010 1135 #define V1 (INSN_4100 | INSN_4111 | INSN_4120) 1136 #define T3 INSN_3900 1137 #define M1 INSN_10000 1138 #define SB1 INSN_SB1 1139 #define N411 INSN_4111 1140 #define N412 INSN_4120 1141 #define N5 (INSN_5400 | INSN_5500) 1142 #define N54 INSN_5400 1143 #define N55 INSN_5500 1144 1145 #define G1 (T3 \ 1146 ) 1147 1148 #define G2 (T3 \ 1149 ) 1150 1151 #define G3 (I4 \ 1152 ) 1153 1154 /* MIPS DSP ASE support. 1155 NOTE: 1156 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair 1157 of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have 1158 the same structure as $ac0 (HI + LO). For DSP instructions that write or 1159 read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a 1160 (RD_HILO) attributes, such that HILO dependencies are maintained 1161 conservatively. 1162 1163 2. For some mul. instructions that use integer registers as destinations 1164 but destroy HI+LO as side-effect, we add WR_HILO to their attributes. 1165 1166 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields 1167 (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write 1168 certain fields of the DSP control register. For simplicity, we decide not 1169 to track dependencies of these fields. 1170 However, "bposge32" is a branch instruction that depends on the "pos" 1171 field. In order to make sure that GAS does not reorder DSP instructions 1172 that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP) 1173 attribute to those instructions that write the "pos" field. */ 1174 1175 #define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */ 1176 #define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */ 1177 #define MOD_a WR_a|RD_a 1178 #define DSP_VOLA INSN_TRAP 1179 #define D32 INSN_DSP 1180 #define D33 INSN_DSPR2 1181 #define D64 INSN_DSP64 1182 1183 /* MIPS MT ASE support. */ 1184 #define MT32 INSN_MT 1185 1186 /* The order of overloaded instructions matters. Label arguments and 1187 register arguments look the same. Instructions that can have either 1188 for arguments must apear in the correct order in this table for the 1189 assembler to pick the right one. In other words, entries with 1190 immediate operands must apear after the same instruction with 1191 registers. 1192 1193 Because of the lookup algorithm used, entries with the same opcode 1194 name must be contiguous. 1195 1196 Many instructions are short hand for other instructions (i.e., The 1197 jal <register> instruction is short for jalr <register>). */ 1198 1199 const struct mips_opcode mips_builtin_opcodes[] = 1200 { 1201 /* These instructions appear first so that the disassembler will find 1202 them first. The assemblers uses a hash table based on the 1203 instruction name anyhow. */ 1204 /* name, args, match, mask, pinfo, membership */ 1205 {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 }, 1206 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 }, 1207 {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ 1208 {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */ 1209 {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */ 1210 {"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */ 1211 {"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */ 1212 {"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 }, 1213 {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 }, 1214 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */ 1215 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */ 1216 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */ 1217 {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */ 1218 {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */ 1219 {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/ 1220 1221 {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, 1222 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1223 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, 1224 {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, 1225 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 1226 {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 }, 1227 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 1228 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 1229 {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1230 {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1231 {"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1232 {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1233 {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 1234 {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1235 {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1236 {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1237 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 1238 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 1239 {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1240 {"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1241 {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 1242 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 1243 {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 }, 1244 {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1245 {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 }, 1246 {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1247 {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 1248 {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 }, 1249 {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX }, 1250 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 1251 {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 }, 1252 {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1253 {"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1254 {"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1255 {"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1256 {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1257 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 1258 /* b is at the top of the table. */ 1259 /* bal is at the top of the table. */ 1260 /* bc0[tf]l? are at the bottom of the table. */ 1261 {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 1262 {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 1263 {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 1264 {"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 1265 {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, 1266 {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, 1267 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, 1268 {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, 1269 {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, 1270 {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, 1271 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, 1272 {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, 1273 /* bc2* are at the bottom of the table. */ 1274 /* bc3* are at the bottom of the table. */ 1275 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1276 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1277 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, 1278 {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, 1279 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, 1280 {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 }, 1281 {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, 1282 {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, 1283 {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 }, 1284 {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 }, 1285 {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, 1286 {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, 1287 {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 }, 1288 {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 }, 1289 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1290 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1291 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, 1292 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, 1293 {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, 1294 {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, 1295 {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 }, 1296 {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 }, 1297 {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, 1298 {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, 1299 {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 }, 1300 {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 }, 1301 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1302 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1303 {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, 1304 {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, 1305 {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 }, 1306 {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 }, 1307 {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, 1308 {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, 1309 {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 }, 1310 {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 }, 1311 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1312 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1313 {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, 1314 {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, 1315 {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 }, 1316 {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 }, 1317 {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, 1318 {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, 1319 {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 }, 1320 {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 }, 1321 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1322 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1323 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, 1324 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, 1325 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1326 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1327 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, 1328 {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, 1329 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, 1330 {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 }, 1331 {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 }, 1332 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 }, 1333 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 }, 1334 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1335 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1336 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1337 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1338 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1339 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1340 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1341 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1342 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1343 {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1344 {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1345 {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1346 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1347 {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1348 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1349 {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1350 {"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1351 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1352 {"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1353 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1354 {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1355 {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1356 {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, 1357 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1358 {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1359 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1360 {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1361 {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1362 {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1363 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1364 {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1365 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1366 {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1367 {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1368 {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1369 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1370 {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1371 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1372 {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1373 {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1374 {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1375 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1376 {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1377 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1378 {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1379 {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1380 {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1381 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1382 {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1383 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1384 {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1385 {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1386 {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1387 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1388 {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1389 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1390 {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1391 {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1392 {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1393 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1394 {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1395 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1396 {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1397 {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1398 {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1399 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1400 {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1401 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1402 {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1403 {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1404 {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1405 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1406 {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1407 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1408 {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1409 {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1410 {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1411 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1412 {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1413 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1414 {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1415 {"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1416 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1417 {"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1418 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1419 {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1420 {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1421 {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, 1422 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1423 {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1424 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1425 {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1426 {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1427 {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1428 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1429 {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1430 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1431 {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1432 {"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1433 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1434 {"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1435 {"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1436 {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1437 {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1438 {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, 1439 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1440 {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1441 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1442 {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1443 {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1444 {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1445 {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1446 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1447 {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1448 {"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1449 {"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1450 {"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1451 {"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1452 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1453 {"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1454 {"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1455 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1456 {"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1457 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1458 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1459 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1460 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1461 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1462 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1463 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1464 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1465 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1466 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1467 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1468 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1469 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1470 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1471 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1472 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1473 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1474 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1475 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1476 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1477 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1478 {"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1479 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1480 {"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1481 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1482 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1483 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1484 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1485 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1486 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1487 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1488 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1489 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1490 {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1491 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1492 {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1493 /* CW4010 instructions which are aliases for the cache instruction. */ 1494 {"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 }, 1495 {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, 1496 {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, 1497 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, 1498 {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3}, 1499 {"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3}, 1500 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 1501 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 1502 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 1503 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 1504 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, 1505 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, 1506 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, 1507 /* cfc2 is at the bottom of the table. */ 1508 /* cfc3 is at the bottom of the table. */ 1509 {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, 1510 {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, 1511 {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, 1512 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, 1513 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, 1514 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, 1515 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, 1516 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, 1517 /* ctc2 is at the bottom of the table. */ 1518 /* ctc3 is at the bottom of the table. */ 1519 {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, 1520 {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, 1521 {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 }, 1522 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 1523 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 1524 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 1525 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 1526 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 1527 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 1528 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 1529 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1530 {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, 1531 {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, 1532 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 1533 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1534 {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, 1535 {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 }, 1536 {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, 1537 {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, 1538 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 1539 {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 }, 1540 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, 1541 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, 1542 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 1543 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, 1544 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 }, 1545 {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, 1546 {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, 1547 /* dctr and dctw are used on the r5000. */ 1548 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 }, 1549 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 }, 1550 {"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 }, 1551 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 }, 1552 {"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1553 {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1554 {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1555 /* For ddiv, see the comments about div. */ 1556 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1557 {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 }, 1558 {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 }, 1559 /* For ddivu, see the comments about div. */ 1560 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1561 {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 }, 1562 {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 }, 1563 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 1564 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 1565 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 }, 1566 {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1567 {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1568 {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1569 /* The MIPS assembler treats the div opcode with two operands as 1570 though the first operand appeared twice (the first operand is both 1571 a source and a destination). To get the div machine instruction, 1572 you must use an explicit destination of $0. */ 1573 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 1574 {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 1575 {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, 1576 {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 }, 1577 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 1578 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 1579 {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, 1580 /* For divu, see the comments about div. */ 1581 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 1582 {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 1583 {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, 1584 {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 }, 1585 {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 }, 1586 {"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 }, 1587 {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */ 1588 {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */ 1589 {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 }, 1590 {"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1591 {"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1592 {"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1593 {"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1594 {"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1595 {"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1596 {"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1597 {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1598 {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 }, 1599 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 }, 1600 {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, 1601 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, 1602 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 }, 1603 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1604 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 }, 1605 {"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, 1606 {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, 1607 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, 1608 {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, 1609 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, 1610 {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, 1611 /* dmfc2 is at the bottom of the table. */ 1612 /* dmtc2 is at the bottom of the table. */ 1613 /* dmfc3 is at the bottom of the table. */ 1614 /* dmtc3 is at the bottom of the table. */ 1615 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, 1616 {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 }, 1617 {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 }, 1618 {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 }, 1619 {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 }, 1620 {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 }, 1621 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1622 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1623 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */ 1624 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/ 1625 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1626 {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 }, 1627 {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 }, 1628 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1629 {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, 1630 {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, 1631 {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, 1632 {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, 1633 {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, 1634 {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 }, 1635 {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 }, 1636 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, 1637 {"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 }, 1638 {"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, 1639 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 }, 1640 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 }, 1641 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 }, 1642 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 }, 1643 {"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 }, 1644 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 }, 1645 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 }, 1646 {"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 }, 1647 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, 1648 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1649 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */ 1650 {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */ 1651 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1652 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, 1653 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1654 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */ 1655 {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */ 1656 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1657 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, 1658 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1659 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */ 1660 {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */ 1661 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1662 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 1663 {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 }, 1664 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 1665 {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 }, 1666 {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 }, 1667 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1668 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 1669 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 1670 {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 }, 1671 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1672 {"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 }, 1673 {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 }, 1674 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1675 {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, 1676 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 1677 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 1678 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 1679 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 1680 {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, 1681 {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, 1682 {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, 1683 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with 1684 the same hazard barrier effect. */ 1685 {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 }, 1686 {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ 1687 /* SVR4 PIC code requires special handling for j, so it must be a 1688 macro. */ 1689 {"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 }, 1690 /* This form of j is used by the disassembler and internally by the 1691 assembler, but will never match user input (because the line above 1692 will match first). */ 1693 {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 }, 1694 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 }, 1695 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 }, 1696 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr 1697 with the same hazard barrier effect. */ 1698 {"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 }, 1699 {"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 }, 1700 /* SVR4 PIC code requires special handling for jal, so it must be a 1701 macro. */ 1702 {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 }, 1703 {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 }, 1704 {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 }, 1705 /* This form of jal is used by the disassembler and internally by the 1706 assembler, but will never match user input (because the line above 1707 will match first). */ 1708 {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 }, 1709 {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 }, 1710 {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 }, 1711 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1712 {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 }, 1713 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1714 {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 }, 1715 {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 }, 1716 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, 1717 {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, 1718 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, 1719 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, 1720 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, 1721 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, 1722 {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, 1723 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */ 1724 {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 }, 1725 {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 }, 1726 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, 1727 {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 }, 1728 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, 1729 {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 }, 1730 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, 1731 {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 }, 1732 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, 1733 {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 }, 1734 {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, 1735 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1736 {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 }, 1737 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1738 {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 }, 1739 /* li is at the start of the table. */ 1740 {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 }, 1741 {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 }, 1742 {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 }, 1743 {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 }, 1744 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, 1745 {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 }, 1746 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, 1747 {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 }, 1748 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, 1749 {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55}, 1750 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1751 {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 }, 1752 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, 1753 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 }, 1754 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, 1755 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, 1756 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, 1757 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, 1758 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */ 1759 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, 1760 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, 1761 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 }, 1762 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, 1763 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 }, 1764 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1765 {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 }, 1766 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ 1767 {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */ 1768 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1769 {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 }, 1770 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ 1771 {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */ 1772 {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 }, 1773 {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, 1774 {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 }, 1775 {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, 1776 {"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT }, 1777 {"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1778 {"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1779 {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1780 {"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1781 {"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1782 {"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1783 {"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1784 {"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1785 {"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1786 {"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1787 {"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1788 {"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1789 {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, 1790 {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, 1791 {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 1792 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 1793 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 1794 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 1795 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 1796 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, 1797 {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 1798 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 1799 {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, 1800 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 1801 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 1802 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, 1803 {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 1804 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 1805 {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 }, 1806 {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1807 {"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1808 {"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1809 {"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1810 {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1811 {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, 1812 {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, 1813 {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, 1814 {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, 1815 {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, 1816 {"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, 1817 {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, 1818 {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, 1819 {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, 1820 {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, 1821 {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 }, 1822 {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, 1823 {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, 1824 {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, 1825 {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, 1826 {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, 1827 {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, 1828 {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, 1829 {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, 1830 {"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 }, 1831 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, 1832 {"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, 1833 {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, 1834 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, 1835 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, 1836 {"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, 1837 {"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, 1838 /* mfc2 is at the bottom of the table. */ 1839 /* mfhc2 is at the bottom of the table. */ 1840 /* mfc3 is at the bottom of the table. */ 1841 {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, 1842 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, 1843 {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, 1844 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, 1845 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, 1846 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, 1847 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1848 {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1849 {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1850 {"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1851 {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1852 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, 1853 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1854 {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, 1855 {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, 1856 {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, 1857 {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 1858 {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 1859 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, 1860 {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, 1861 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, 1862 {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, 1863 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, 1864 {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 1865 {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 1866 {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, 1867 {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, 1868 {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, 1869 {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, 1870 {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 1871 {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 1872 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, 1873 {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, 1874 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, 1875 {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, 1876 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, 1877 {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 1878 {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 1879 {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, 1880 {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, 1881 {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1882 {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1883 {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1884 {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1885 /* move is at the top of the table. */ 1886 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1887 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 1888 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 1889 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 1890 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 1891 {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 1892 {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 1893 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 1894 {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 1895 {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 1896 {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, 1897 {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, 1898 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 }, 1899 {"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, 1900 {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, 1901 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, 1902 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, 1903 {"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, 1904 {"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, 1905 /* mtc2 is at the bottom of the table. */ 1906 /* mthc2 is at the bottom of the table. */ 1907 /* mtc3 is at the bottom of the table. */ 1908 {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, 1909 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, 1910 {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, 1911 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, 1912 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, 1913 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, 1914 {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, 1915 {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, 1916 {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, 1917 {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, 1918 {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, 1919 {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, 1920 {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, 1921 {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, 1922 {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 }, 1923 {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, 1924 {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, 1925 {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, 1926 {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, 1927 {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, 1928 {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, 1929 {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, 1930 {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, 1931 {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 }, 1932 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 1933 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 1934 {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1935 {"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1936 {"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1937 {"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1938 {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 1939 {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1940 {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55}, 1941 {"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 }, 1942 {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 }, 1943 {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 }, 1944 {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1945 {"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1946 {"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1947 {"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1948 {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1949 {"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1950 {"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1951 {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1952 {"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1953 {"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1954 {"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1955 {"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1956 {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 }, 1957 {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 }, 1958 {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 }, 1959 {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 }, 1960 {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 1961 {"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1962 {"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1963 {"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1964 {"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1965 {"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1966 {"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1967 {"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1968 {"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1969 {"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1970 {"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1971 {"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1972 {"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1973 {"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1974 {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1975 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, 1976 {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, 1977 {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 1978 {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, 1979 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, 1980 {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, 1981 {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 1982 {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1983 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ 1984 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */ 1985 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, 1986 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1987 {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, 1988 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 1989 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 1990 {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 1991 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 1992 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 1993 {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 1994 /* nop is at the start of the table. */ 1995 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 1996 {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 }, 1997 {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1998 {"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1999 {"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2000 {"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2001 {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2002 {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/ 2003 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2004 {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 }, 2005 {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2006 {"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2007 {"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2008 {"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2009 {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2010 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2011 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, 2012 {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 }, 2013 {"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, 2014 {"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2015 {"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2016 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2017 {"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2018 {"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2019 {"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2020 {"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2021 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2022 {"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2023 {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2024 {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2025 {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2026 /* pref and prefx are at the start of the table. */ 2027 {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2028 {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2029 {"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT }, 2030 {"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, 2031 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 2032 {"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, 2033 {"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, 2034 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 2035 {"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, 2036 {"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, 2037 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 2038 {"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, 2039 {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, 2040 {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, 2041 {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, 2042 {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, 2043 {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2044 {"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2045 {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 2046 {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2047 {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2048 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 2049 {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 }, 2050 {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 }, 2051 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 2052 {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 }, 2053 {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 }, 2054 {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 }, 2055 {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 }, 2056 {"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 }, 2057 {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2058 {"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, 2059 {"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2060 {"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2061 {"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, 2062 {"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2063 {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 }, 2064 {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, 2065 {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, 2066 {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, 2067 {"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT }, 2068 {"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT }, 2069 {"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT }, 2070 {"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT }, 2071 {"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT }, 2072 {"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT }, 2073 {"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT }, 2074 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 2075 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 2076 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 2077 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2078 {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, 2079 {"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, 2080 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, 2081 {"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, 2082 {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2083 {"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2084 {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 2085 {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2086 {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2087 {"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2088 {"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, 2089 {"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 }, 2090 {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2091 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2092 {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 }, 2093 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 }, 2094 {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 }, 2095 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 }, 2096 {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 }, 2097 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, 2098 {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 }, 2099 {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 }, 2100 {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 }, 2101 {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 }, 2102 {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 }, 2103 {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 }, 2104 {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 }, 2105 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, 2106 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, 2107 {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, 2108 {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, 2109 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 }, 2110 {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 }, 2111 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 }, 2112 {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 }, 2113 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, 2114 {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 }, 2115 {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 }, 2116 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, 2117 {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, 2118 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, 2119 {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 }, 2120 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4|I33 }, 2121 {"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 }, 2122 {"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 }, 2123 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, 2124 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, 2125 {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 }, 2126 {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 }, 2127 {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 }, 2128 {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 }, 2129 {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 }, 2130 {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 }, 2131 {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 }, 2132 {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 }, 2133 {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 }, 2134 {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 }, 2135 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2136 {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 }, 2137 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2138 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2139 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2140 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2141 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2142 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2143 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2144 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2145 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2146 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2147 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2148 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2149 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2150 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2151 {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 }, 2152 {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 }, 2153 {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 }, 2154 {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 }, 2155 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, 2156 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */ 2157 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 }, 2158 {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2159 {"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2160 {"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2161 {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2162 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2163 {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 }, 2164 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2165 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2166 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2167 {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 }, 2168 {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 }, 2169 {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 }, 2170 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, 2171 {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2172 {"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, 2173 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, 2174 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */ 2175 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 }, 2176 {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2177 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, 2178 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */ 2179 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 }, 2180 {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2181 {"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2182 {"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2183 {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2184 /* ssnop is at the start of the table. */ 2185 {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 }, 2186 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2187 {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 }, 2188 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 2189 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 2190 {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2191 {"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2192 {"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2193 {"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2194 {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2195 {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2196 {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2197 {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2198 {"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2199 {"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2200 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2201 {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, 2202 {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 }, 2203 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55}, 2204 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2205 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 }, 2206 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 }, 2207 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 }, 2208 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, 2209 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, 2210 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, 2211 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, 2212 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */ 2213 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, 2214 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, 2215 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, 2216 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 }, 2217 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 }, 2218 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2219 {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 }, 2220 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ 2221 {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */ 2222 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2223 {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 }, 2224 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ 2225 {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */ 2226 {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 }, 2227 {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 }, 2228 {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 }, 2229 {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 }, 2230 {"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 }, 2231 {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 }, 2232 {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 }, 2233 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2234 {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2235 {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2236 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */ 2237 {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 }, 2238 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2239 {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2240 {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2241 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */ 2242 {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 }, 2243 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2244 {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2245 {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2246 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */ 2247 {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 }, 2248 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 }, 2249 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 }, 2250 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 }, 2251 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 }, 2252 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2253 {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2254 {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2255 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */ 2256 {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 }, 2257 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2258 {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2259 {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2260 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */ 2261 {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 }, 2262 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2263 {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2264 {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2265 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */ 2266 {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 }, 2267 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 2268 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 2269 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 2270 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 2271 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 }, 2272 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2273 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2274 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 }, 2275 {"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 }, 2276 {"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 }, 2277 {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 }, 2278 {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 }, 2279 {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 }, 2280 {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 }, 2281 {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 }, 2282 {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 }, 2283 {"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 }, 2284 {"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 }, 2285 {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 }, 2286 {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 }, 2287 {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 }, 2288 {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 }, 2289 {"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 }, 2290 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, 2291 {"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX }, 2292 {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2293 {"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 }, 2294 {"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2295 {"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3|I32 }, 2296 {"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 }, 2297 {"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 }, 2298 {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, 2299 {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, 2300 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2301 {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, 2302 {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2303 {"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2304 {"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2305 {"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2306 {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2307 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2308 {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 }, 2309 {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 }, 2310 2311 /* User Defined Instruction. */ 2312 {"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2313 {"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2314 {"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2315 {"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2316 {"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2317 {"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2318 {"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2319 {"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2320 {"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2321 {"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2322 {"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2323 {"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2324 {"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2325 {"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2326 {"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2327 {"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2328 {"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2329 {"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2330 {"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2331 {"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2332 {"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2333 {"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2334 {"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2335 {"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2336 {"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2337 {"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2338 {"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2339 {"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2340 {"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2341 {"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2342 {"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2343 {"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2344 {"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2345 {"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2346 {"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2347 {"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2348 {"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2349 {"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2350 {"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2351 {"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2352 {"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2353 {"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2354 {"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2355 {"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2356 {"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2357 {"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2358 {"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2359 {"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2360 {"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2361 {"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2362 {"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2363 {"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2364 {"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2365 {"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2366 {"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2367 {"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2368 {"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2369 {"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2370 {"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2371 {"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2372 {"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2373 {"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2374 {"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2375 {"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2376 2377 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format 2378 instructions so they are here for the latters to take precedence. */ 2379 {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2380 {"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 }, 2381 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2382 {"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 }, 2383 {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2384 {"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 }, 2385 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2386 {"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 }, 2387 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, 2388 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, 2389 {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 }, 2390 {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 }, 2391 {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 }, 2392 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 }, 2393 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, 2394 {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 }, 2395 {"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 }, 2396 {"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 }, 2397 {"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 }, 2398 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 }, 2399 {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 }, 2400 {"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 }, 2401 {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 }, 2402 {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 }, 2403 2404 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X 2405 instructions, so they are here for the latters to take precedence. */ 2406 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2407 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2408 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2409 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2410 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, 2411 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, 2412 {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 }, 2413 {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 }, 2414 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, 2415 {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, 2416 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, 2417 {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, 2418 2419 /* No hazard protection on coprocessor instructions--they shouldn't 2420 change the state of the processor and if they do it's up to the 2421 user to put in nops as necessary. These are at the end so that the 2422 disassembler recognizes more specific versions first. */ 2423 {"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 }, 2424 {"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 }, 2425 {"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 }, 2426 {"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 }, 2427 {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 }, 2428 {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 }, 2429 {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 }, 2430 {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }, 2431 /* Conflicts with the 4650's "mul" instruction. Nobody's using the 2432 4010 any more, so move this insn out of the way. If the object 2433 format gave us more info, we could do this right. */ 2434 {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 }, 2435 /* MIPS DSP ASE */ 2436 {"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2437 {"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2438 {"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2439 {"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2440 {"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2441 {"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2442 {"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2443 {"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2444 {"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2445 {"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2446 {"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2447 {"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2448 {"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2449 {"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2450 {"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2451 {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2452 {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2453 {"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2454 {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 }, 2455 {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 }, 2456 {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2457 {"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2458 {"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2459 {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2460 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2461 {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2462 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2463 {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2464 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2465 {"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2466 {"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2467 {"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2468 {"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2469 {"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2470 {"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2471 {"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2472 {"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2473 {"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2474 {"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2475 {"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2476 {"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2477 {"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 }, 2478 {"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 }, 2479 {"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2480 {"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2481 {"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2482 {"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2483 {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2484 {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2485 {"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2486 {"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2487 {"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2488 {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2489 {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2490 {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2491 {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2492 {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2493 {"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2494 {"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2495 {"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 }, 2496 {"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2497 {"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2498 {"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2499 {"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2500 {"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 }, 2501 {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2502 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2503 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2504 {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2505 {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2506 {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2507 {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2508 {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2509 {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2510 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2511 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2512 {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2513 {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2514 {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2515 {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2516 {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2517 {"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 }, 2518 {"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 }, 2519 {"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 }, 2520 {"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 }, 2521 {"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2522 {"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2523 {"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2524 {"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2525 {"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2526 {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2527 {"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2528 {"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2529 {"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2530 {"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2531 {"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, 2532 {"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, 2533 {"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 }, 2534 {"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, 2535 {"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, 2536 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2537 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2538 {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2539 {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2540 {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2541 {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2542 {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2543 {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2544 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2545 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2546 {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2547 {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2548 {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2549 {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2550 {"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2551 {"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 }, 2552 {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2553 {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2554 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2555 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2556 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2557 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2558 {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2559 {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2560 {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2561 {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2562 {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2563 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2564 {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2565 {"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2566 {"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2567 {"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2568 {"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2569 {"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2570 {"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2571 {"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2572 {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2573 {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2574 {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2575 {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2576 {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2577 {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2578 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2579 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2580 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2581 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2582 {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2583 {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2584 {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2585 {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2586 {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2587 {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2588 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2589 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2590 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2591 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2592 {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2593 {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2594 {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2595 {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2596 {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2597 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2598 {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2599 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2600 {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2601 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2602 {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2603 {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2604 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2605 {"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 }, 2606 {"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 }, 2607 {"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 }, 2608 {"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 }, 2609 {"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 }, 2610 {"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 }, 2611 {"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 }, 2612 {"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 }, 2613 {"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 }, 2614 {"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2615 {"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2616 {"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2617 {"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2618 {"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2619 {"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 }, 2620 {"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 }, 2621 {"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 }, 2622 {"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 2623 {"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 2624 {"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 }, 2625 {"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 2626 {"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 2627 {"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 2628 {"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 2629 {"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 }, 2630 {"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2631 {"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2632 {"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2633 {"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2634 {"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2635 {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2636 {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2637 {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2638 {"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2639 {"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 2640 {"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 2641 {"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 2642 {"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 2643 {"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 2644 {"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 2645 {"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 }, 2646 {"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2647 {"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2648 {"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2649 {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2650 {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2651 {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2652 {"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2653 {"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 }, 2654 {"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 }, 2655 {"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2656 {"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2657 {"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2658 {"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2659 {"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2660 {"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2661 {"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2662 {"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2663 {"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2664 {"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2665 {"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2666 {"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2667 {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2668 {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 }, 2669 {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 }, 2670 /* MIPS DSP ASE Rev2 */ 2671 {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 }, 2672 {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2673 {"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2674 {"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2675 {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2676 {"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 2677 {"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 }, 2678 {"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 }, 2679 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2680 {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2681 {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2682 {"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2683 {"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2684 {"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2685 {"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2686 {"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2687 {"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2688 {"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2689 {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2690 {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2691 {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 2692 {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 2693 {"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 2694 {"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 }, 2695 {"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 }, 2696 {"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2697 {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2698 {"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 }, 2699 {"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2700 {"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2701 {"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2702 {"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2703 {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2704 {"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2705 {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2706 {"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2707 {"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2708 {"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2709 {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2710 {"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2711 {"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2712 {"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2713 {"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2714 {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2715 {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2716 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2717 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2718 /* Move bc0* after mftr and mttr to avoid opcode collision. */ 2719 {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2720 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2721 {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2722 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2723 }; 2724 2725 #define MIPS_NUM_OPCODES \ 2726 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) 2727 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; 2728 2729 /* const removed from the following to allow for dynamic extensions to the 2730 * built-in instruction set. */ 2731 struct mips_opcode *mips_opcodes = 2732 (struct mips_opcode *) mips_builtin_opcodes; 2733 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; 2734 #undef MIPS_NUM_OPCODES 2735 2736 /* Mips instructions are at maximum this many bytes long. */ 2737 #define INSNLEN 4 2738 2739 2740 /* FIXME: These should be shared with gdb somehow. */ 2742 2743 struct mips_cp0sel_name 2744 { 2745 unsigned int cp0reg; 2746 unsigned int sel; 2747 const char * const name; 2748 }; 2749 2750 /* The mips16 registers. */ 2751 static const unsigned int mips16_to_32_reg_map[] = 2752 { 2753 16, 17, 2, 3, 4, 5, 6, 7 2754 }; 2755 2756 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] 2757 2758 2759 static const char * const mips_gpr_names_numeric[32] = 2760 { 2761 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 2762 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 2763 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 2764 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 2765 }; 2766 2767 static const char * const mips_gpr_names_oldabi[32] = 2768 { 2769 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 2770 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 2771 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2772 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 2773 }; 2774 2775 static const char * const mips_gpr_names_newabi[32] = 2776 { 2777 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 2778 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 2779 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2780 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 2781 }; 2782 2783 static const char * const mips_fpr_names_numeric[32] = 2784 { 2785 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 2786 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 2787 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 2788 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" 2789 }; 2790 2791 static const char * const mips_fpr_names_32[32] = 2792 { 2793 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", 2794 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", 2795 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", 2796 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" 2797 }; 2798 2799 static const char * const mips_fpr_names_n32[32] = 2800 { 2801 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", 2802 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 2803 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", 2804 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" 2805 }; 2806 2807 static const char * const mips_fpr_names_64[32] = 2808 { 2809 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", 2810 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 2811 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", 2812 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" 2813 }; 2814 2815 static const char * const mips_cp0_names_numeric[32] = 2816 { 2817 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 2818 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 2819 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 2820 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 2821 }; 2822 2823 static const char * const mips_cp0_names_mips3264[32] = 2824 { 2825 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 2826 "c0_context", "c0_pagemask", "c0_wired", "$7", 2827 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 2828 "c0_status", "c0_cause", "c0_epc", "c0_prid", 2829 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 2830 "c0_xcontext", "$21", "$22", "c0_debug", 2831 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 2832 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 2833 }; 2834 2835 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = 2836 { 2837 { 4, 1, "c0_contextconfig" }, 2838 { 0, 1, "c0_mvpcontrol" }, 2839 { 0, 2, "c0_mvpconf0" }, 2840 { 0, 3, "c0_mvpconf1" }, 2841 { 1, 1, "c0_vpecontrol" }, 2842 { 1, 2, "c0_vpeconf0" }, 2843 { 1, 3, "c0_vpeconf1" }, 2844 { 1, 4, "c0_yqmask" }, 2845 { 1, 5, "c0_vpeschedule" }, 2846 { 1, 6, "c0_vpeschefback" }, 2847 { 2, 1, "c0_tcstatus" }, 2848 { 2, 2, "c0_tcbind" }, 2849 { 2, 3, "c0_tcrestart" }, 2850 { 2, 4, "c0_tchalt" }, 2851 { 2, 5, "c0_tccontext" }, 2852 { 2, 6, "c0_tcschedule" }, 2853 { 2, 7, "c0_tcschefback" }, 2854 { 5, 1, "c0_pagegrain" }, 2855 { 6, 1, "c0_srsconf0" }, 2856 { 6, 2, "c0_srsconf1" }, 2857 { 6, 3, "c0_srsconf2" }, 2858 { 6, 4, "c0_srsconf3" }, 2859 { 6, 5, "c0_srsconf4" }, 2860 { 12, 1, "c0_intctl" }, 2861 { 12, 2, "c0_srsctl" }, 2862 { 12, 3, "c0_srsmap" }, 2863 { 15, 1, "c0_ebase" }, 2864 { 16, 1, "c0_config1" }, 2865 { 16, 2, "c0_config2" }, 2866 { 16, 3, "c0_config3" }, 2867 { 18, 1, "c0_watchlo,1" }, 2868 { 18, 2, "c0_watchlo,2" }, 2869 { 18, 3, "c0_watchlo,3" }, 2870 { 18, 4, "c0_watchlo,4" }, 2871 { 18, 5, "c0_watchlo,5" }, 2872 { 18, 6, "c0_watchlo,6" }, 2873 { 18, 7, "c0_watchlo,7" }, 2874 { 19, 1, "c0_watchhi,1" }, 2875 { 19, 2, "c0_watchhi,2" }, 2876 { 19, 3, "c0_watchhi,3" }, 2877 { 19, 4, "c0_watchhi,4" }, 2878 { 19, 5, "c0_watchhi,5" }, 2879 { 19, 6, "c0_watchhi,6" }, 2880 { 19, 7, "c0_watchhi,7" }, 2881 { 23, 1, "c0_tracecontrol" }, 2882 { 23, 2, "c0_tracecontrol2" }, 2883 { 23, 3, "c0_usertracedata" }, 2884 { 23, 4, "c0_tracebpc" }, 2885 { 25, 1, "c0_perfcnt,1" }, 2886 { 25, 2, "c0_perfcnt,2" }, 2887 { 25, 3, "c0_perfcnt,3" }, 2888 { 25, 4, "c0_perfcnt,4" }, 2889 { 25, 5, "c0_perfcnt,5" }, 2890 { 25, 6, "c0_perfcnt,6" }, 2891 { 25, 7, "c0_perfcnt,7" }, 2892 { 27, 1, "c0_cacheerr,1" }, 2893 { 27, 2, "c0_cacheerr,2" }, 2894 { 27, 3, "c0_cacheerr,3" }, 2895 { 28, 1, "c0_datalo" }, 2896 { 28, 2, "c0_taglo1" }, 2897 { 28, 3, "c0_datalo1" }, 2898 { 28, 4, "c0_taglo2" }, 2899 { 28, 5, "c0_datalo2" }, 2900 { 28, 6, "c0_taglo3" }, 2901 { 28, 7, "c0_datalo3" }, 2902 { 29, 1, "c0_datahi" }, 2903 { 29, 2, "c0_taghi1" }, 2904 { 29, 3, "c0_datahi1" }, 2905 { 29, 4, "c0_taghi2" }, 2906 { 29, 5, "c0_datahi2" }, 2907 { 29, 6, "c0_taghi3" }, 2908 { 29, 7, "c0_datahi3" }, 2909 }; 2910 2911 static const char * const mips_cp0_names_mips3264r2[32] = 2912 { 2913 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 2914 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", 2915 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 2916 "c0_status", "c0_cause", "c0_epc", "c0_prid", 2917 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 2918 "c0_xcontext", "$21", "$22", "c0_debug", 2919 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 2920 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 2921 }; 2922 2923 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = 2924 { 2925 { 4, 1, "c0_contextconfig" }, 2926 { 5, 1, "c0_pagegrain" }, 2927 { 12, 1, "c0_intctl" }, 2928 { 12, 2, "c0_srsctl" }, 2929 { 12, 3, "c0_srsmap" }, 2930 { 15, 1, "c0_ebase" }, 2931 { 16, 1, "c0_config1" }, 2932 { 16, 2, "c0_config2" }, 2933 { 16, 3, "c0_config3" }, 2934 { 18, 1, "c0_watchlo,1" }, 2935 { 18, 2, "c0_watchlo,2" }, 2936 { 18, 3, "c0_watchlo,3" }, 2937 { 18, 4, "c0_watchlo,4" }, 2938 { 18, 5, "c0_watchlo,5" }, 2939 { 18, 6, "c0_watchlo,6" }, 2940 { 18, 7, "c0_watchlo,7" }, 2941 { 19, 1, "c0_watchhi,1" }, 2942 { 19, 2, "c0_watchhi,2" }, 2943 { 19, 3, "c0_watchhi,3" }, 2944 { 19, 4, "c0_watchhi,4" }, 2945 { 19, 5, "c0_watchhi,5" }, 2946 { 19, 6, "c0_watchhi,6" }, 2947 { 19, 7, "c0_watchhi,7" }, 2948 { 23, 1, "c0_tracecontrol" }, 2949 { 23, 2, "c0_tracecontrol2" }, 2950 { 23, 3, "c0_usertracedata" }, 2951 { 23, 4, "c0_tracebpc" }, 2952 { 25, 1, "c0_perfcnt,1" }, 2953 { 25, 2, "c0_perfcnt,2" }, 2954 { 25, 3, "c0_perfcnt,3" }, 2955 { 25, 4, "c0_perfcnt,4" }, 2956 { 25, 5, "c0_perfcnt,5" }, 2957 { 25, 6, "c0_perfcnt,6" }, 2958 { 25, 7, "c0_perfcnt,7" }, 2959 { 27, 1, "c0_cacheerr,1" }, 2960 { 27, 2, "c0_cacheerr,2" }, 2961 { 27, 3, "c0_cacheerr,3" }, 2962 { 28, 1, "c0_datalo" }, 2963 { 28, 2, "c0_taglo1" }, 2964 { 28, 3, "c0_datalo1" }, 2965 { 28, 4, "c0_taglo2" }, 2966 { 28, 5, "c0_datalo2" }, 2967 { 28, 6, "c0_taglo3" }, 2968 { 28, 7, "c0_datalo3" }, 2969 { 29, 1, "c0_datahi" }, 2970 { 29, 2, "c0_taghi1" }, 2971 { 29, 3, "c0_datahi1" }, 2972 { 29, 4, "c0_taghi2" }, 2973 { 29, 5, "c0_datahi2" }, 2974 { 29, 6, "c0_taghi3" }, 2975 { 29, 7, "c0_datahi3" }, 2976 }; 2977 2978 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ 2979 static const char * const mips_cp0_names_sb1[32] = 2980 { 2981 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 2982 "c0_context", "c0_pagemask", "c0_wired", "$7", 2983 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 2984 "c0_status", "c0_cause", "c0_epc", "c0_prid", 2985 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 2986 "c0_xcontext", "$21", "$22", "c0_debug", 2987 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 2988 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 2989 }; 2990 2991 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = 2992 { 2993 { 16, 1, "c0_config1" }, 2994 { 18, 1, "c0_watchlo,1" }, 2995 { 19, 1, "c0_watchhi,1" }, 2996 { 22, 0, "c0_perftrace" }, 2997 { 23, 3, "c0_edebug" }, 2998 { 25, 1, "c0_perfcnt,1" }, 2999 { 25, 2, "c0_perfcnt,2" }, 3000 { 25, 3, "c0_perfcnt,3" }, 3001 { 25, 4, "c0_perfcnt,4" }, 3002 { 25, 5, "c0_perfcnt,5" }, 3003 { 25, 6, "c0_perfcnt,6" }, 3004 { 25, 7, "c0_perfcnt,7" }, 3005 { 26, 1, "c0_buserr_pa" }, 3006 { 27, 1, "c0_cacheerr_d" }, 3007 { 27, 3, "c0_cacheerr_d_pa" }, 3008 { 28, 1, "c0_datalo_i" }, 3009 { 28, 2, "c0_taglo_d" }, 3010 { 28, 3, "c0_datalo_d" }, 3011 { 29, 1, "c0_datahi_i" }, 3012 { 29, 2, "c0_taghi_d" }, 3013 { 29, 3, "c0_datahi_d" }, 3014 }; 3015 3016 static const char * const mips_hwr_names_numeric[32] = 3017 { 3018 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 3019 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3020 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3021 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 3022 }; 3023 3024 static const char * const mips_hwr_names_mips3264r2[32] = 3025 { 3026 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", 3027 "$4", "$5", "$6", "$7", 3028 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3029 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3030 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 3031 }; 3032 3033 struct mips_abi_choice 3034 { 3035 const char *name; 3036 const char * const *gpr_names; 3037 const char * const *fpr_names; 3038 }; 3039 3040 struct mips_abi_choice mips_abi_choices[] = 3041 { 3042 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, 3043 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, 3044 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, 3045 { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, 3046 }; 3047 3048 struct mips_arch_choice 3049 { 3050 const char *name; 3051 int bfd_mach_valid; 3052 unsigned long bfd_mach; 3053 int processor; 3054 int isa; 3055 const char * const *cp0_names; 3056 const struct mips_cp0sel_name *cp0sel_names; 3057 unsigned int cp0sel_names_len; 3058 const char * const *hwr_names; 3059 }; 3060 3061 #define bfd_mach_mips3000 3000 3062 #define bfd_mach_mips3900 3900 3063 #define bfd_mach_mips4000 4000 3064 #define bfd_mach_mips4010 4010 3065 #define bfd_mach_mips4100 4100 3066 #define bfd_mach_mips4111 4111 3067 #define bfd_mach_mips4120 4120 3068 #define bfd_mach_mips4300 4300 3069 #define bfd_mach_mips4400 4400 3070 #define bfd_mach_mips4600 4600 3071 #define bfd_mach_mips4650 4650 3072 #define bfd_mach_mips5000 5000 3073 #define bfd_mach_mips5400 5400 3074 #define bfd_mach_mips5500 5500 3075 #define bfd_mach_mips6000 6000 3076 #define bfd_mach_mips7000 7000 3077 #define bfd_mach_mips8000 8000 3078 #define bfd_mach_mips9000 9000 3079 #define bfd_mach_mips10000 10000 3080 #define bfd_mach_mips12000 12000 3081 #define bfd_mach_mips16 16 3082 #define bfd_mach_mips5 5 3083 #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */ 3084 #define bfd_mach_mipsisa32 32 3085 #define bfd_mach_mipsisa32r2 33 3086 #define bfd_mach_mipsisa64 64 3087 #define bfd_mach_mipsisa64r2 65 3088 3089 #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) 3090 3091 const struct mips_arch_choice mips_arch_choices[] = 3092 { 3093 { "numeric", 0, 0, 0, 0, 3094 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3095 3096 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 3097 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3098 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 3099 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3100 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 3101 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3102 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 3103 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3104 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 3105 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3106 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 3107 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3108 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 3109 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3110 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 3111 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3112 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 3113 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3114 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 3115 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3116 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 3117 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3118 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 3119 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3120 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 3121 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3122 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 3123 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3124 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 3125 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3126 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 3127 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3128 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 3129 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3130 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 3131 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3132 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 3133 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3134 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 3135 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3136 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 3137 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3138 3139 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. 3140 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See 3141 _MIPS32 Architecture For Programmers Volume I: Introduction to the 3142 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), 3143 page 1. */ 3144 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, 3145 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS, 3146 mips_cp0_names_mips3264, 3147 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 3148 mips_hwr_names_numeric }, 3149 3150 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, 3151 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 3152 | INSN_MIPS3D | INSN_MT), 3153 mips_cp0_names_mips3264r2, 3154 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 3155 mips_hwr_names_mips3264r2 }, 3156 3157 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ 3158 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, 3159 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, 3160 mips_cp0_names_mips3264, 3161 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 3162 mips_hwr_names_numeric }, 3163 3164 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, 3165 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 3166 | INSN_DSP64 | INSN_MT | INSN_MDMX), 3167 mips_cp0_names_mips3264r2, 3168 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 3169 mips_hwr_names_mips3264r2 }, 3170 3171 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, 3172 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, 3173 mips_cp0_names_sb1, 3174 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), 3175 mips_hwr_names_numeric }, 3176 3177 /* This entry, mips16, is here only for ISA/processor selection; do 3178 not print its name. */ 3179 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, 3180 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3181 }; 3182 3183 /* ISA and processor type to disassemble for, and register names to use. 3184 set_default_mips_dis_options and parse_mips_dis_options fill in these 3185 values. */ 3186 static int mips_processor; 3187 static int mips_isa; 3188 static const char * const *mips_gpr_names; 3189 static const char * const *mips_fpr_names; 3190 static const char * const *mips_cp0_names; 3191 static const struct mips_cp0sel_name *mips_cp0sel_names; 3192 static int mips_cp0sel_names_len; 3193 static const char * const *mips_hwr_names; 3194 3195 /* Other options */ 3196 static int no_aliases; /* If set disassemble as most general inst. */ 3197 3198 static const struct mips_abi_choice * 3200 choose_abi_by_name (const char *name, unsigned int namelen) 3201 { 3202 const struct mips_abi_choice *c; 3203 unsigned int i; 3204 3205 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) 3206 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 3207 && strlen (mips_abi_choices[i].name) == namelen) 3208 c = &mips_abi_choices[i]; 3209 3210 return c; 3211 } 3212 3213 static const struct mips_arch_choice * 3214 choose_arch_by_name (const char *name, unsigned int namelen) 3215 { 3216 const struct mips_arch_choice *c = NULL; 3217 unsigned int i; 3218 3219 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 3220 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 3221 && strlen (mips_arch_choices[i].name) == namelen) 3222 c = &mips_arch_choices[i]; 3223 3224 return c; 3225 } 3226 3227 static const struct mips_arch_choice * 3228 choose_arch_by_number (unsigned long mach) 3229 { 3230 static unsigned long hint_bfd_mach; 3231 static const struct mips_arch_choice *hint_arch_choice; 3232 const struct mips_arch_choice *c; 3233 unsigned int i; 3234 3235 /* We optimize this because even if the user specifies no 3236 flags, this will be done for every instruction! */ 3237 if (hint_bfd_mach == mach 3238 && hint_arch_choice != NULL 3239 && hint_arch_choice->bfd_mach == hint_bfd_mach) 3240 return hint_arch_choice; 3241 3242 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 3243 { 3244 if (mips_arch_choices[i].bfd_mach_valid 3245 && mips_arch_choices[i].bfd_mach == mach) 3246 { 3247 c = &mips_arch_choices[i]; 3248 hint_bfd_mach = mach; 3249 hint_arch_choice = c; 3250 } 3251 } 3252 return c; 3253 } 3254 3255 static void 3256 set_default_mips_dis_options (struct disassemble_info *info) 3257 { 3258 const struct mips_arch_choice *chosen_arch; 3259 3260 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, 3261 and numeric FPR, CP0 register, and HWR names. */ 3262 mips_isa = ISA_MIPS3; 3263 mips_processor = CPU_R3000; 3264 mips_gpr_names = mips_gpr_names_oldabi; 3265 mips_fpr_names = mips_fpr_names_numeric; 3266 mips_cp0_names = mips_cp0_names_numeric; 3267 mips_cp0sel_names = NULL; 3268 mips_cp0sel_names_len = 0; 3269 mips_hwr_names = mips_hwr_names_numeric; 3270 no_aliases = 0; 3271 3272 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ 3273 #if 0 3274 if (info->flavour == bfd_target_elf_flavour && info->section != NULL) 3275 { 3276 Elf_Internal_Ehdr *header; 3277 3278 header = elf_elfheader (info->section->owner); 3279 if (is_newabi (header)) 3280 mips_gpr_names = mips_gpr_names_newabi; 3281 } 3282 #endif 3283 3284 /* Set ISA, architecture, and cp0 register names as best we can. */ 3285 #if !defined(SYMTAB_AVAILABLE) && 0 3286 /* This is running out on a target machine, not in a host tool. 3287 FIXME: Where does mips_target_info come from? */ 3288 target_processor = mips_target_info.processor; 3289 mips_isa = mips_target_info.isa; 3290 #else 3291 chosen_arch = choose_arch_by_number (info->mach); 3292 if (chosen_arch != NULL) 3293 { 3294 mips_processor = chosen_arch->processor; 3295 mips_isa = chosen_arch->isa; 3296 mips_cp0_names = chosen_arch->cp0_names; 3297 mips_cp0sel_names = chosen_arch->cp0sel_names; 3298 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 3299 mips_hwr_names = chosen_arch->hwr_names; 3300 } 3301 #endif 3302 } 3303 3304 static void 3305 parse_mips_dis_option (const char *option, unsigned int len) 3306 { 3307 unsigned int i, optionlen, vallen; 3308 const char *val; 3309 const struct mips_abi_choice *chosen_abi; 3310 const struct mips_arch_choice *chosen_arch; 3311 3312 /* Look for the = that delimits the end of the option name. */ 3313 for (i = 0; i < len; i++) 3314 { 3315 if (option[i] == '=') 3316 break; 3317 } 3318 if (i == 0) /* Invalid option: no name before '='. */ 3319 return; 3320 if (i == len) /* Invalid option: no '='. */ 3321 return; 3322 if (i == (len - 1)) /* Invalid option: no value after '='. */ 3323 return; 3324 3325 optionlen = i; 3326 val = option + (optionlen + 1); 3327 vallen = len - (optionlen + 1); 3328 3329 if (strncmp("gpr-names", option, optionlen) == 0 3330 && strlen("gpr-names") == optionlen) 3331 { 3332 chosen_abi = choose_abi_by_name (val, vallen); 3333 if (chosen_abi != NULL) 3334 mips_gpr_names = chosen_abi->gpr_names; 3335 return; 3336 } 3337 3338 if (strncmp("fpr-names", option, optionlen) == 0 3339 && strlen("fpr-names") == optionlen) 3340 { 3341 chosen_abi = choose_abi_by_name (val, vallen); 3342 if (chosen_abi != NULL) 3343 mips_fpr_names = chosen_abi->fpr_names; 3344 return; 3345 } 3346 3347 if (strncmp("cp0-names", option, optionlen) == 0 3348 && strlen("cp0-names") == optionlen) 3349 { 3350 chosen_arch = choose_arch_by_name (val, vallen); 3351 if (chosen_arch != NULL) 3352 { 3353 mips_cp0_names = chosen_arch->cp0_names; 3354 mips_cp0sel_names = chosen_arch->cp0sel_names; 3355 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 3356 } 3357 return; 3358 } 3359 3360 if (strncmp("hwr-names", option, optionlen) == 0 3361 && strlen("hwr-names") == optionlen) 3362 { 3363 chosen_arch = choose_arch_by_name (val, vallen); 3364 if (chosen_arch != NULL) 3365 mips_hwr_names = chosen_arch->hwr_names; 3366 return; 3367 } 3368 3369 if (strncmp("reg-names", option, optionlen) == 0 3370 && strlen("reg-names") == optionlen) 3371 { 3372 /* We check both ABI and ARCH here unconditionally, so 3373 that "numeric" will do the desirable thing: select 3374 numeric register names for all registers. Other than 3375 that, a given name probably won't match both. */ 3376 chosen_abi = choose_abi_by_name (val, vallen); 3377 if (chosen_abi != NULL) 3378 { 3379 mips_gpr_names = chosen_abi->gpr_names; 3380 mips_fpr_names = chosen_abi->fpr_names; 3381 } 3382 chosen_arch = choose_arch_by_name (val, vallen); 3383 if (chosen_arch != NULL) 3384 { 3385 mips_cp0_names = chosen_arch->cp0_names; 3386 mips_cp0sel_names = chosen_arch->cp0sel_names; 3387 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 3388 mips_hwr_names = chosen_arch->hwr_names; 3389 } 3390 return; 3391 } 3392 3393 /* Invalid option. */ 3394 } 3395 3396 static void 3397 parse_mips_dis_options (const char *options) 3398 { 3399 const char *option_end; 3400 3401 if (options == NULL) 3402 return; 3403 3404 while (*options != '\0') 3405 { 3406 /* Skip empty options. */ 3407 if (*options == ',') 3408 { 3409 options++; 3410 continue; 3411 } 3412 3413 /* We know that *options is neither NUL or a comma. */ 3414 option_end = options + 1; 3415 while (*option_end != ',' && *option_end != '\0') 3416 option_end++; 3417 3418 parse_mips_dis_option (options, option_end - options); 3419 3420 /* Go on to the next one. If option_end points to a comma, it 3421 will be skipped above. */ 3422 options = option_end; 3423 } 3424 } 3425 3426 static const struct mips_cp0sel_name * 3427 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, 3428 unsigned int len, 3429 unsigned int cp0reg, 3430 unsigned int sel) 3431 { 3432 unsigned int i; 3433 3434 for (i = 0; i < len; i++) 3435 if (names[i].cp0reg == cp0reg && names[i].sel == sel) 3436 return &names[i]; 3437 return NULL; 3438 } 3439 3440 /* Print insn arguments for 32/64-bit code. */ 3442 3443 static void 3444 print_insn_args (const char *d, 3445 register unsigned long int l, 3446 bfd_vma pc, 3447 struct disassemble_info *info, 3448 const struct mips_opcode *opp) 3449 { 3450 int op, delta; 3451 unsigned int lsb, msb, msbd; 3452 3453 lsb = 0; 3454 3455 for (; *d != '\0'; d++) 3456 { 3457 switch (*d) 3458 { 3459 case ',': 3460 case '(': 3461 case ')': 3462 case '[': 3463 case ']': 3464 (*info->fprintf_func) (info->stream, "%c", *d); 3465 break; 3466 3467 case '+': 3468 /* Extension character; switch for second char. */ 3469 d++; 3470 switch (*d) 3471 { 3472 case '\0': 3473 /* xgettext:c-format */ 3474 (*info->fprintf_func) (info->stream, 3475 _("# internal error, incomplete extension sequence (+)")); 3476 return; 3477 3478 case 'A': 3479 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; 3480 (*info->fprintf_func) (info->stream, "0x%x", lsb); 3481 break; 3482 3483 case 'B': 3484 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; 3485 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 3486 break; 3487 3488 case '1': 3489 (*info->fprintf_func) (info->stream, "0x%lx", 3490 (l >> OP_SH_UDI1) & OP_MASK_UDI1); 3491 break; 3492 3493 case '2': 3494 (*info->fprintf_func) (info->stream, "0x%lx", 3495 (l >> OP_SH_UDI2) & OP_MASK_UDI2); 3496 break; 3497 3498 case '3': 3499 (*info->fprintf_func) (info->stream, "0x%lx", 3500 (l >> OP_SH_UDI3) & OP_MASK_UDI3); 3501 break; 3502 3503 case '4': 3504 (*info->fprintf_func) (info->stream, "0x%lx", 3505 (l >> OP_SH_UDI4) & OP_MASK_UDI4); 3506 break; 3507 3508 case 'C': 3509 case 'H': 3510 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; 3511 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 3512 break; 3513 3514 case 'D': 3515 { 3516 const struct mips_cp0sel_name *n; 3517 unsigned int cp0reg, sel; 3518 3519 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; 3520 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 3521 3522 /* CP0 register including 'sel' code for mtcN (et al.), to be 3523 printed textually if known. If not known, print both 3524 CP0 register name and sel numerically since CP0 register 3525 with sel 0 may have a name unrelated to register being 3526 printed. */ 3527 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 3528 mips_cp0sel_names_len, cp0reg, sel); 3529 if (n != NULL) 3530 (*info->fprintf_func) (info->stream, "%s", n->name); 3531 else 3532 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 3533 break; 3534 } 3535 3536 case 'E': 3537 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; 3538 (*info->fprintf_func) (info->stream, "0x%x", lsb); 3539 break; 3540 3541 case 'F': 3542 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; 3543 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 3544 break; 3545 3546 case 'G': 3547 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; 3548 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 3549 break; 3550 3551 case 't': /* Coprocessor 0 reg name */ 3552 (*info->fprintf_func) (info->stream, "%s", 3553 mips_cp0_names[(l >> OP_SH_RT) & 3554 OP_MASK_RT]); 3555 break; 3556 3557 case 'T': /* Coprocessor 0 reg name */ 3558 { 3559 const struct mips_cp0sel_name *n; 3560 unsigned int cp0reg, sel; 3561 3562 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; 3563 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 3564 3565 /* CP0 register including 'sel' code for mftc0, to be 3566 printed textually if known. If not known, print both 3567 CP0 register name and sel numerically since CP0 register 3568 with sel 0 may have a name unrelated to register being 3569 printed. */ 3570 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 3571 mips_cp0sel_names_len, cp0reg, sel); 3572 if (n != NULL) 3573 (*info->fprintf_func) (info->stream, "%s", n->name); 3574 else 3575 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 3576 break; 3577 } 3578 3579 default: 3580 /* xgettext:c-format */ 3581 (*info->fprintf_func) (info->stream, 3582 _("# internal error, undefined extension sequence (+%c)"), 3583 *d); 3584 return; 3585 } 3586 break; 3587 3588 case '2': 3589 (*info->fprintf_func) (info->stream, "0x%lx", 3590 (l >> OP_SH_BP) & OP_MASK_BP); 3591 break; 3592 3593 case '3': 3594 (*info->fprintf_func) (info->stream, "0x%lx", 3595 (l >> OP_SH_SA3) & OP_MASK_SA3); 3596 break; 3597 3598 case '4': 3599 (*info->fprintf_func) (info->stream, "0x%lx", 3600 (l >> OP_SH_SA4) & OP_MASK_SA4); 3601 break; 3602 3603 case '5': 3604 (*info->fprintf_func) (info->stream, "0x%lx", 3605 (l >> OP_SH_IMM8) & OP_MASK_IMM8); 3606 break; 3607 3608 case '6': 3609 (*info->fprintf_func) (info->stream, "0x%lx", 3610 (l >> OP_SH_RS) & OP_MASK_RS); 3611 break; 3612 3613 case '7': 3614 (*info->fprintf_func) (info->stream, "$ac%ld", 3615 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC); 3616 break; 3617 3618 case '8': 3619 (*info->fprintf_func) (info->stream, "0x%lx", 3620 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP); 3621 break; 3622 3623 case '9': 3624 (*info->fprintf_func) (info->stream, "$ac%ld", 3625 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S); 3626 break; 3627 3628 case '0': /* dsp 6-bit signed immediate in bit 20 */ 3629 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT); 3630 if (delta & 0x20) /* test sign bit */ 3631 delta |= ~OP_MASK_DSPSFT; 3632 (*info->fprintf_func) (info->stream, "%d", delta); 3633 break; 3634 3635 case ':': /* dsp 7-bit signed immediate in bit 19 */ 3636 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7); 3637 if (delta & 0x40) /* test sign bit */ 3638 delta |= ~OP_MASK_DSPSFT_7; 3639 (*info->fprintf_func) (info->stream, "%d", delta); 3640 break; 3641 3642 case '\'': 3643 (*info->fprintf_func) (info->stream, "0x%lx", 3644 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP); 3645 break; 3646 3647 case '@': /* dsp 10-bit signed immediate in bit 16 */ 3648 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); 3649 if (delta & 0x200) /* test sign bit */ 3650 delta |= ~OP_MASK_IMM10; 3651 (*info->fprintf_func) (info->stream, "%d", delta); 3652 break; 3653 3654 case '!': 3655 (*info->fprintf_func) (info->stream, "%ld", 3656 (l >> OP_SH_MT_U) & OP_MASK_MT_U); 3657 break; 3658 3659 case '$': 3660 (*info->fprintf_func) (info->stream, "%ld", 3661 (l >> OP_SH_MT_H) & OP_MASK_MT_H); 3662 break; 3663 3664 case '*': 3665 (*info->fprintf_func) (info->stream, "$ac%ld", 3666 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); 3667 break; 3668 3669 case '&': 3670 (*info->fprintf_func) (info->stream, "$ac%ld", 3671 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); 3672 break; 3673 3674 case 'g': 3675 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ 3676 (*info->fprintf_func) (info->stream, "$%ld", 3677 (l >> OP_SH_RD) & OP_MASK_RD); 3678 break; 3679 3680 case 's': 3681 case 'b': 3682 case 'r': 3683 case 'v': 3684 (*info->fprintf_func) (info->stream, "%s", 3685 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); 3686 break; 3687 3688 case 't': 3689 case 'w': 3690 (*info->fprintf_func) (info->stream, "%s", 3691 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 3692 break; 3693 3694 case 'i': 3695 case 'u': 3696 (*info->fprintf_func) (info->stream, "0x%lx", 3697 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); 3698 break; 3699 3700 case 'j': /* Same as i, but sign-extended. */ 3701 case 'o': 3702 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 3703 if (delta & 0x8000) 3704 delta |= ~0xffff; 3705 (*info->fprintf_func) (info->stream, "%d", 3706 delta); 3707 break; 3708 3709 case 'h': 3710 (*info->fprintf_func) (info->stream, "0x%x", 3711 (unsigned int) ((l >> OP_SH_PREFX) 3712 & OP_MASK_PREFX)); 3713 break; 3714 3715 case 'k': 3716 (*info->fprintf_func) (info->stream, "0x%x", 3717 (unsigned int) ((l >> OP_SH_CACHE) 3718 & OP_MASK_CACHE)); 3719 break; 3720 3721 case 'a': 3722 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) 3723 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); 3724 /* For gdb disassembler, force odd address on jalx. */ 3725 if (info->flavour == bfd_target_unknown_flavour 3726 && strcmp (opp->name, "jalx") == 0) 3727 info->target |= 1; 3728 (*info->print_address_func) (info->target, info); 3729 break; 3730 3731 case 'p': 3732 /* Sign extend the displacement. */ 3733 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 3734 if (delta & 0x8000) 3735 delta |= ~0xffff; 3736 info->target = (delta << 2) + pc + INSNLEN; 3737 (*info->print_address_func) (info->target, info); 3738 break; 3739 3740 case 'd': 3741 (*info->fprintf_func) (info->stream, "%s", 3742 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 3743 break; 3744 3745 case 'U': 3746 { 3747 /* First check for both rd and rt being equal. */ 3748 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; 3749 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) 3750 (*info->fprintf_func) (info->stream, "%s", 3751 mips_gpr_names[reg]); 3752 else 3753 { 3754 /* If one is zero use the other. */ 3755 if (reg == 0) 3756 (*info->fprintf_func) (info->stream, "%s", 3757 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 3758 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) 3759 (*info->fprintf_func) (info->stream, "%s", 3760 mips_gpr_names[reg]); 3761 else /* Bogus, result depends on processor. */ 3762 (*info->fprintf_func) (info->stream, "%s or %s", 3763 mips_gpr_names[reg], 3764 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 3765 } 3766 } 3767 break; 3768 3769 case 'z': 3770 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 3771 break; 3772 3773 case '<': 3774 (*info->fprintf_func) (info->stream, "0x%lx", 3775 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); 3776 break; 3777 3778 case 'c': 3779 (*info->fprintf_func) (info->stream, "0x%lx", 3780 (l >> OP_SH_CODE) & OP_MASK_CODE); 3781 break; 3782 3783 case 'q': 3784 (*info->fprintf_func) (info->stream, "0x%lx", 3785 (l >> OP_SH_CODE2) & OP_MASK_CODE2); 3786 break; 3787 3788 case 'C': 3789 (*info->fprintf_func) (info->stream, "0x%lx", 3790 (l >> OP_SH_COPZ) & OP_MASK_COPZ); 3791 break; 3792 3793 case 'B': 3794 (*info->fprintf_func) (info->stream, "0x%lx", 3795 3796 (l >> OP_SH_CODE20) & OP_MASK_CODE20); 3797 break; 3798 3799 case 'J': 3800 (*info->fprintf_func) (info->stream, "0x%lx", 3801 (l >> OP_SH_CODE19) & OP_MASK_CODE19); 3802 break; 3803 3804 case 'S': 3805 case 'V': 3806 (*info->fprintf_func) (info->stream, "%s", 3807 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); 3808 break; 3809 3810 case 'T': 3811 case 'W': 3812 (*info->fprintf_func) (info->stream, "%s", 3813 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); 3814 break; 3815 3816 case 'D': 3817 (*info->fprintf_func) (info->stream, "%s", 3818 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); 3819 break; 3820 3821 case 'R': 3822 (*info->fprintf_func) (info->stream, "%s", 3823 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); 3824 break; 3825 3826 case 'E': 3827 /* Coprocessor register for lwcN instructions, et al. 3828 3829 Note that there is no load/store cp0 instructions, and 3830 that FPU (cp1) instructions disassemble this field using 3831 'T' format. Therefore, until we gain understanding of 3832 cp2 register names, we can simply print the register 3833 numbers. */ 3834 (*info->fprintf_func) (info->stream, "$%ld", 3835 (l >> OP_SH_RT) & OP_MASK_RT); 3836 break; 3837 3838 case 'G': 3839 /* Coprocessor register for mtcN instructions, et al. Note 3840 that FPU (cp1) instructions disassemble this field using 3841 'S' format. Therefore, we only need to worry about cp0, 3842 cp2, and cp3. */ 3843 op = (l >> OP_SH_OP) & OP_MASK_OP; 3844 if (op == OP_OP_COP0) 3845 (*info->fprintf_func) (info->stream, "%s", 3846 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); 3847 else 3848 (*info->fprintf_func) (info->stream, "$%ld", 3849 (l >> OP_SH_RD) & OP_MASK_RD); 3850 break; 3851 3852 case 'K': 3853 (*info->fprintf_func) (info->stream, "%s", 3854 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 3855 break; 3856 3857 case 'N': 3858 (*info->fprintf_func) (info->stream, 3859 ((opp->pinfo & (FP_D | FP_S)) != 0 3860 ? "$fcc%ld" : "$cc%ld"), 3861 (l >> OP_SH_BCC) & OP_MASK_BCC); 3862 break; 3863 3864 case 'M': 3865 (*info->fprintf_func) (info->stream, "$fcc%ld", 3866 (l >> OP_SH_CCC) & OP_MASK_CCC); 3867 break; 3868 3869 case 'P': 3870 (*info->fprintf_func) (info->stream, "%ld", 3871 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); 3872 break; 3873 3874 case 'e': 3875 (*info->fprintf_func) (info->stream, "%ld", 3876 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); 3877 break; 3878 3879 case '%': 3880 (*info->fprintf_func) (info->stream, "%ld", 3881 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); 3882 break; 3883 3884 case 'H': 3885 (*info->fprintf_func) (info->stream, "%ld", 3886 (l >> OP_SH_SEL) & OP_MASK_SEL); 3887 break; 3888 3889 case 'O': 3890 (*info->fprintf_func) (info->stream, "%ld", 3891 (l >> OP_SH_ALN) & OP_MASK_ALN); 3892 break; 3893 3894 case 'Q': 3895 { 3896 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; 3897 3898 if ((vsel & 0x10) == 0) 3899 { 3900 int fmt; 3901 3902 vsel &= 0x0f; 3903 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) 3904 if ((vsel & 1) == 0) 3905 break; 3906 (*info->fprintf_func) (info->stream, "$v%ld[%d]", 3907 (l >> OP_SH_FT) & OP_MASK_FT, 3908 vsel >> 1); 3909 } 3910 else if ((vsel & 0x08) == 0) 3911 { 3912 (*info->fprintf_func) (info->stream, "$v%ld", 3913 (l >> OP_SH_FT) & OP_MASK_FT); 3914 } 3915 else 3916 { 3917 (*info->fprintf_func) (info->stream, "0x%lx", 3918 (l >> OP_SH_FT) & OP_MASK_FT); 3919 } 3920 } 3921 break; 3922 3923 case 'X': 3924 (*info->fprintf_func) (info->stream, "$v%ld", 3925 (l >> OP_SH_FD) & OP_MASK_FD); 3926 break; 3927 3928 case 'Y': 3929 (*info->fprintf_func) (info->stream, "$v%ld", 3930 (l >> OP_SH_FS) & OP_MASK_FS); 3931 break; 3932 3933 case 'Z': 3934 (*info->fprintf_func) (info->stream, "$v%ld", 3935 (l >> OP_SH_FT) & OP_MASK_FT); 3936 break; 3937 3938 default: 3939 /* xgettext:c-format */ 3940 (*info->fprintf_func) (info->stream, 3941 _("# internal error, undefined modifier(%c)"), 3942 *d); 3943 return; 3944 } 3945 } 3946 } 3947 3948 /* Check if the object uses NewABI conventions. */ 3950 #if 0 3951 static int 3952 is_newabi (header) 3953 Elf_Internal_Ehdr *header; 3954 { 3955 /* There are no old-style ABIs which use 64-bit ELF. */ 3956 if (header->e_ident[EI_CLASS] == ELFCLASS64) 3957 return 1; 3958 3959 /* If a 32-bit ELF file, n32 is a new-style ABI. */ 3960 if ((header->e_flags & EF_MIPS_ABI2) != 0) 3961 return 1; 3962 3963 return 0; 3964 } 3965 #endif 3966 3967 /* Print the mips instruction at address MEMADDR in debugged memory, 3969 on using INFO. Returns length of the instruction, in bytes, which is 3970 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if 3971 this is little-endian code. */ 3972 3973 static int 3974 print_insn_mips (bfd_vma memaddr, 3975 unsigned long int word, 3976 struct disassemble_info *info) 3977 { 3978 const struct mips_opcode *op; 3979 static bfd_boolean init = 0; 3980 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; 3981 3982 /* Build a hash table to shorten the search time. */ 3983 if (! init) 3984 { 3985 unsigned int i; 3986 3987 for (i = 0; i <= OP_MASK_OP; i++) 3988 { 3989 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) 3990 { 3991 if (op->pinfo == INSN_MACRO 3992 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 3993 continue; 3994 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) 3995 { 3996 mips_hash[i] = op; 3997 break; 3998 } 3999 } 4000 } 4001 4002 init = 1; 4003 } 4004 4005 info->bytes_per_chunk = INSNLEN; 4006 info->display_endian = info->endian; 4007 info->insn_info_valid = 1; 4008 info->branch_delay_insns = 0; 4009 info->data_size = 0; 4010 info->insn_type = dis_nonbranch; 4011 info->target = 0; 4012 info->target2 = 0; 4013 4014 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; 4015 if (op != NULL) 4016 { 4017 for (; op < &mips_opcodes[NUMOPCODES]; op++) 4018 { 4019 if (op->pinfo != INSN_MACRO 4020 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 4021 && (word & op->mask) == op->match) 4022 { 4023 const char *d; 4024 4025 /* We always allow to disassemble the jalx instruction. */ 4026 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) 4027 && strcmp (op->name, "jalx")) 4028 continue; 4029 4030 /* Figure out instruction type and branch delay information. */ 4031 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 4032 { 4033 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) 4034 info->insn_type = dis_jsr; 4035 else 4036 info->insn_type = dis_branch; 4037 info->branch_delay_insns = 1; 4038 } 4039 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY 4040 | INSN_COND_BRANCH_LIKELY)) != 0) 4041 { 4042 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) 4043 info->insn_type = dis_condjsr; 4044 else 4045 info->insn_type = dis_condbranch; 4046 info->branch_delay_insns = 1; 4047 } 4048 else if ((op->pinfo & (INSN_STORE_MEMORY 4049 | INSN_LOAD_MEMORY_DELAY)) != 0) 4050 info->insn_type = dis_dref; 4051 4052 (*info->fprintf_func) (info->stream, "%s", op->name); 4053 4054 d = op->args; 4055 if (d != NULL && *d != '\0') 4056 { 4057 (*info->fprintf_func) (info->stream, "\t"); 4058 print_insn_args (d, word, memaddr, info, op); 4059 } 4060 4061 return INSNLEN; 4062 } 4063 } 4064 } 4065 4066 /* Handle undefined instructions. */ 4067 info->insn_type = dis_noninsn; 4068 (*info->fprintf_func) (info->stream, "0x%lx", word); 4069 return INSNLEN; 4070 } 4071 4072 /* In an environment where we do not know the symbol type of the 4074 instruction we are forced to assume that the low order bit of the 4075 instructions' address may mark it as a mips16 instruction. If we 4076 are single stepping, or the pc is within the disassembled function, 4077 this works. Otherwise, we need a clue. Sometimes. */ 4078 4079 static int 4080 _print_insn_mips (bfd_vma memaddr, 4081 struct disassemble_info *info, 4082 enum bfd_endian endianness) 4083 { 4084 bfd_byte buffer[INSNLEN]; 4085 int status; 4086 4087 set_default_mips_dis_options (info); 4088 parse_mips_dis_options (info->disassembler_options); 4089 4090 #if 0 4091 #if 1 4092 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ 4093 /* Only a few tools will work this way. */ 4094 if (memaddr & 0x01) 4095 return print_insn_mips16 (memaddr, info); 4096 #endif 4097 4098 #if SYMTAB_AVAILABLE 4099 if (info->mach == bfd_mach_mips16 4100 || (info->flavour == bfd_target_elf_flavour 4101 && info->symbols != NULL 4102 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other 4103 == STO_MIPS16))) 4104 return print_insn_mips16 (memaddr, info); 4105 #endif 4106 #endif 4107 4108 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); 4109 if (status == 0) 4110 { 4111 unsigned long insn; 4112 4113 if (endianness == BFD_ENDIAN_BIG) 4114 insn = (unsigned long) bfd_getb32 (buffer); 4115 else 4116 insn = (unsigned long) bfd_getl32 (buffer); 4117 4118 return print_insn_mips (memaddr, insn, info); 4119 } 4120 else 4121 { 4122 (*info->memory_error_func) (status, memaddr, info); 4123 return -1; 4124 } 4125 } 4126 4127 int 4128 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) 4129 { 4130 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); 4131 } 4132 4133 int 4134 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) 4135 { 4136 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); 4137 } 4138 4139 /* Disassemble mips16 instructions. */ 4141 #if 0 4142 static int 4143 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) 4144 { 4145 int status; 4146 bfd_byte buffer[2]; 4147 int length; 4148 int insn; 4149 bfd_boolean use_extend; 4150 int extend = 0; 4151 const struct mips_opcode *op, *opend; 4152 4153 info->bytes_per_chunk = 2; 4154 info->display_endian = info->endian; 4155 info->insn_info_valid = 1; 4156 info->branch_delay_insns = 0; 4157 info->data_size = 0; 4158 info->insn_type = dis_nonbranch; 4159 info->target = 0; 4160 info->target2 = 0; 4161 4162 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 4163 if (status != 0) 4164 { 4165 (*info->memory_error_func) (status, memaddr, info); 4166 return -1; 4167 } 4168 4169 length = 2; 4170 4171 if (info->endian == BFD_ENDIAN_BIG) 4172 insn = bfd_getb16 (buffer); 4173 else 4174 insn = bfd_getl16 (buffer); 4175 4176 /* Handle the extend opcode specially. */ 4177 use_extend = FALSE; 4178 if ((insn & 0xf800) == 0xf000) 4179 { 4180 use_extend = TRUE; 4181 extend = insn & 0x7ff; 4182 4183 memaddr += 2; 4184 4185 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 4186 if (status != 0) 4187 { 4188 (*info->fprintf_func) (info->stream, "extend 0x%x", 4189 (unsigned int) extend); 4190 (*info->memory_error_func) (status, memaddr, info); 4191 return -1; 4192 } 4193 4194 if (info->endian == BFD_ENDIAN_BIG) 4195 insn = bfd_getb16 (buffer); 4196 else 4197 insn = bfd_getl16 (buffer); 4198 4199 /* Check for an extend opcode followed by an extend opcode. */ 4200 if ((insn & 0xf800) == 0xf000) 4201 { 4202 (*info->fprintf_func) (info->stream, "extend 0x%x", 4203 (unsigned int) extend); 4204 info->insn_type = dis_noninsn; 4205 return length; 4206 } 4207 4208 length += 2; 4209 } 4210 4211 /* FIXME: Should probably use a hash table on the major opcode here. */ 4212 4213 opend = mips16_opcodes + bfd_mips16_num_opcodes; 4214 for (op = mips16_opcodes; op < opend; op++) 4215 { 4216 if (op->pinfo != INSN_MACRO 4217 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 4218 && (insn & op->mask) == op->match) 4219 { 4220 const char *s; 4221 4222 if (strchr (op->args, 'a') != NULL) 4223 { 4224 if (use_extend) 4225 { 4226 (*info->fprintf_func) (info->stream, "extend 0x%x", 4227 (unsigned int) extend); 4228 info->insn_type = dis_noninsn; 4229 return length - 2; 4230 } 4231 4232 use_extend = FALSE; 4233 4234 memaddr += 2; 4235 4236 status = (*info->read_memory_func) (memaddr, buffer, 2, 4237 info); 4238 if (status == 0) 4239 { 4240 use_extend = TRUE; 4241 if (info->endian == BFD_ENDIAN_BIG) 4242 extend = bfd_getb16 (buffer); 4243 else 4244 extend = bfd_getl16 (buffer); 4245 length += 2; 4246 } 4247 } 4248 4249 (*info->fprintf_func) (info->stream, "%s", op->name); 4250 if (op->args[0] != '\0') 4251 (*info->fprintf_func) (info->stream, "\t"); 4252 4253 for (s = op->args; *s != '\0'; s++) 4254 { 4255 if (*s == ',' 4256 && s[1] == 'w' 4257 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) 4258 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) 4259 { 4260 /* Skip the register and the comma. */ 4261 ++s; 4262 continue; 4263 } 4264 if (*s == ',' 4265 && s[1] == 'v' 4266 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) 4267 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) 4268 { 4269 /* Skip the register and the comma. */ 4270 ++s; 4271 continue; 4272 } 4273 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, 4274 info); 4275 } 4276 4277 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 4278 { 4279 info->branch_delay_insns = 1; 4280 if (info->insn_type != dis_jsr) 4281 info->insn_type = dis_branch; 4282 } 4283 4284 return length; 4285 } 4286 } 4287 4288 if (use_extend) 4289 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); 4290 (*info->fprintf_func) (info->stream, "0x%x", insn); 4291 info->insn_type = dis_noninsn; 4292 4293 return length; 4294 } 4295 4296 /* Disassemble an operand for a mips16 instruction. */ 4297 4298 static void 4299 print_mips16_insn_arg (char type, 4300 const struct mips_opcode *op, 4301 int l, 4302 bfd_boolean use_extend, 4303 int extend, 4304 bfd_vma memaddr, 4305 struct disassemble_info *info) 4306 { 4307 switch (type) 4308 { 4309 case ',': 4310 case '(': 4311 case ')': 4312 (*info->fprintf_func) (info->stream, "%c", type); 4313 break; 4314 4315 case 'y': 4316 case 'w': 4317 (*info->fprintf_func) (info->stream, "%s", 4318 mips16_reg_names(((l >> MIPS16OP_SH_RY) 4319 & MIPS16OP_MASK_RY))); 4320 break; 4321 4322 case 'x': 4323 case 'v': 4324 (*info->fprintf_func) (info->stream, "%s", 4325 mips16_reg_names(((l >> MIPS16OP_SH_RX) 4326 & MIPS16OP_MASK_RX))); 4327 break; 4328 4329 case 'z': 4330 (*info->fprintf_func) (info->stream, "%s", 4331 mips16_reg_names(((l >> MIPS16OP_SH_RZ) 4332 & MIPS16OP_MASK_RZ))); 4333 break; 4334 4335 case 'Z': 4336 (*info->fprintf_func) (info->stream, "%s", 4337 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z) 4338 & MIPS16OP_MASK_MOVE32Z))); 4339 break; 4340 4341 case '0': 4342 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 4343 break; 4344 4345 case 'S': 4346 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); 4347 break; 4348 4349 case 'P': 4350 (*info->fprintf_func) (info->stream, "$pc"); 4351 break; 4352 4353 case 'R': 4354 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); 4355 break; 4356 4357 case 'X': 4358 (*info->fprintf_func) (info->stream, "%s", 4359 mips_gpr_names[((l >> MIPS16OP_SH_REGR32) 4360 & MIPS16OP_MASK_REGR32)]); 4361 break; 4362 4363 case 'Y': 4364 (*info->fprintf_func) (info->stream, "%s", 4365 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); 4366 break; 4367 4368 case '<': 4369 case '>': 4370 case '[': 4371 case ']': 4372 case '4': 4373 case '5': 4374 case 'H': 4375 case 'W': 4376 case 'D': 4377 case 'j': 4378 case '6': 4379 case '8': 4380 case 'V': 4381 case 'C': 4382 case 'U': 4383 case 'k': 4384 case 'K': 4385 case 'p': 4386 case 'q': 4387 case 'A': 4388 case 'B': 4389 case 'E': 4390 { 4391 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; 4392 4393 shift = 0; 4394 signedp = 0; 4395 extbits = 16; 4396 pcrel = 0; 4397 extu = 0; 4398 branch = 0; 4399 switch (type) 4400 { 4401 case '<': 4402 nbits = 3; 4403 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 4404 extbits = 5; 4405 extu = 1; 4406 break; 4407 case '>': 4408 nbits = 3; 4409 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 4410 extbits = 5; 4411 extu = 1; 4412 break; 4413 case '[': 4414 nbits = 3; 4415 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 4416 extbits = 6; 4417 extu = 1; 4418 break; 4419 case ']': 4420 nbits = 3; 4421 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 4422 extbits = 6; 4423 extu = 1; 4424 break; 4425 case '4': 4426 nbits = 4; 4427 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; 4428 signedp = 1; 4429 extbits = 15; 4430 break; 4431 case '5': 4432 nbits = 5; 4433 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4434 info->insn_type = dis_dref; 4435 info->data_size = 1; 4436 break; 4437 case 'H': 4438 nbits = 5; 4439 shift = 1; 4440 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4441 info->insn_type = dis_dref; 4442 info->data_size = 2; 4443 break; 4444 case 'W': 4445 nbits = 5; 4446 shift = 2; 4447 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4448 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 4449 && (op->pinfo & MIPS16_INSN_READ_SP) == 0) 4450 { 4451 info->insn_type = dis_dref; 4452 info->data_size = 4; 4453 } 4454 break; 4455 case 'D': 4456 nbits = 5; 4457 shift = 3; 4458 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4459 info->insn_type = dis_dref; 4460 info->data_size = 8; 4461 break; 4462 case 'j': 4463 nbits = 5; 4464 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4465 signedp = 1; 4466 break; 4467 case '6': 4468 nbits = 6; 4469 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 4470 break; 4471 case '8': 4472 nbits = 8; 4473 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4474 break; 4475 case 'V': 4476 nbits = 8; 4477 shift = 2; 4478 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4479 /* FIXME: This might be lw, or it might be addiu to $sp or 4480 $pc. We assume it's load. */ 4481 info->insn_type = dis_dref; 4482 info->data_size = 4; 4483 break; 4484 case 'C': 4485 nbits = 8; 4486 shift = 3; 4487 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4488 info->insn_type = dis_dref; 4489 info->data_size = 8; 4490 break; 4491 case 'U': 4492 nbits = 8; 4493 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4494 extu = 1; 4495 break; 4496 case 'k': 4497 nbits = 8; 4498 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4499 signedp = 1; 4500 break; 4501 case 'K': 4502 nbits = 8; 4503 shift = 3; 4504 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4505 signedp = 1; 4506 break; 4507 case 'p': 4508 nbits = 8; 4509 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4510 signedp = 1; 4511 pcrel = 1; 4512 branch = 1; 4513 info->insn_type = dis_condbranch; 4514 break; 4515 case 'q': 4516 nbits = 11; 4517 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; 4518 signedp = 1; 4519 pcrel = 1; 4520 branch = 1; 4521 info->insn_type = dis_branch; 4522 break; 4523 case 'A': 4524 nbits = 8; 4525 shift = 2; 4526 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4527 pcrel = 1; 4528 /* FIXME: This can be lw or la. We assume it is lw. */ 4529 info->insn_type = dis_dref; 4530 info->data_size = 4; 4531 break; 4532 case 'B': 4533 nbits = 5; 4534 shift = 3; 4535 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4536 pcrel = 1; 4537 info->insn_type = dis_dref; 4538 info->data_size = 8; 4539 break; 4540 case 'E': 4541 nbits = 5; 4542 shift = 2; 4543 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4544 pcrel = 1; 4545 break; 4546 default: 4547 abort (); 4548 } 4549 4550 if (! use_extend) 4551 { 4552 if (signedp && immed >= (1 << (nbits - 1))) 4553 immed -= 1 << nbits; 4554 immed <<= shift; 4555 if ((type == '<' || type == '>' || type == '[' || type == ']') 4556 && immed == 0) 4557 immed = 8; 4558 } 4559 else 4560 { 4561 if (extbits == 16) 4562 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); 4563 else if (extbits == 15) 4564 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); 4565 else 4566 immed = ((extend >> 6) & 0x1f) | (extend & 0x20); 4567 immed &= (1 << extbits) - 1; 4568 if (! extu && immed >= (1 << (extbits - 1))) 4569 immed -= 1 << extbits; 4570 } 4571 4572 if (! pcrel) 4573 (*info->fprintf_func) (info->stream, "%d", immed); 4574 else 4575 { 4576 bfd_vma baseaddr; 4577 4578 if (branch) 4579 { 4580 immed *= 2; 4581 baseaddr = memaddr + 2; 4582 } 4583 else if (use_extend) 4584 baseaddr = memaddr - 2; 4585 else 4586 { 4587 int status; 4588 bfd_byte buffer[2]; 4589 4590 baseaddr = memaddr; 4591 4592 /* If this instruction is in the delay slot of a jr 4593 instruction, the base address is the address of the 4594 jr instruction. If it is in the delay slot of jalr 4595 instruction, the base address is the address of the 4596 jalr instruction. This test is unreliable: we have 4597 no way of knowing whether the previous word is 4598 instruction or data. */ 4599 status = (*info->read_memory_func) (memaddr - 4, buffer, 2, 4600 info); 4601 if (status == 0 4602 && (((info->endian == BFD_ENDIAN_BIG 4603 ? bfd_getb16 (buffer) 4604 : bfd_getl16 (buffer)) 4605 & 0xf800) == 0x1800)) 4606 baseaddr = memaddr - 4; 4607 else 4608 { 4609 status = (*info->read_memory_func) (memaddr - 2, buffer, 4610 2, info); 4611 if (status == 0 4612 && (((info->endian == BFD_ENDIAN_BIG 4613 ? bfd_getb16 (buffer) 4614 : bfd_getl16 (buffer)) 4615 & 0xf81f) == 0xe800)) 4616 baseaddr = memaddr - 2; 4617 } 4618 } 4619 info->target = (baseaddr & ~((1 << shift) - 1)) + immed; 4620 if (pcrel && branch 4621 && info->flavour == bfd_target_unknown_flavour) 4622 /* For gdb disassembler, maintain odd address. */ 4623 info->target |= 1; 4624 (*info->print_address_func) (info->target, info); 4625 } 4626 } 4627 break; 4628 4629 case 'a': 4630 { 4631 int jalx = l & 0x400; 4632 4633 if (! use_extend) 4634 extend = 0; 4635 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); 4636 if (!jalx && info->flavour == bfd_target_unknown_flavour) 4637 /* For gdb disassembler, maintain odd address. */ 4638 l |= 1; 4639 } 4640 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; 4641 (*info->print_address_func) (info->target, info); 4642 info->insn_type = dis_jsr; 4643 info->branch_delay_insns = 1; 4644 break; 4645 4646 case 'l': 4647 case 'L': 4648 { 4649 int need_comma, amask, smask; 4650 4651 need_comma = 0; 4652 4653 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 4654 4655 amask = (l >> 3) & 7; 4656 4657 if (amask > 0 && amask < 5) 4658 { 4659 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 4660 if (amask > 1) 4661 (*info->fprintf_func) (info->stream, "-%s", 4662 mips_gpr_names[amask + 3]); 4663 need_comma = 1; 4664 } 4665 4666 smask = (l >> 1) & 3; 4667 if (smask == 3) 4668 { 4669 (*info->fprintf_func) (info->stream, "%s??", 4670 need_comma ? "," : ""); 4671 need_comma = 1; 4672 } 4673 else if (smask > 0) 4674 { 4675 (*info->fprintf_func) (info->stream, "%s%s", 4676 need_comma ? "," : "", 4677 mips_gpr_names[16]); 4678 if (smask > 1) 4679 (*info->fprintf_func) (info->stream, "-%s", 4680 mips_gpr_names[smask + 15]); 4681 need_comma = 1; 4682 } 4683 4684 if (l & 1) 4685 { 4686 (*info->fprintf_func) (info->stream, "%s%s", 4687 need_comma ? "," : "", 4688 mips_gpr_names[31]); 4689 need_comma = 1; 4690 } 4691 4692 if (amask == 5 || amask == 6) 4693 { 4694 (*info->fprintf_func) (info->stream, "%s$f0", 4695 need_comma ? "," : ""); 4696 if (amask == 6) 4697 (*info->fprintf_func) (info->stream, "-$f1"); 4698 } 4699 } 4700 break; 4701 4702 case 'm': 4703 case 'M': 4704 /* MIPS16e save/restore. */ 4705 { 4706 int need_comma = 0; 4707 int amask, args, statics; 4708 int nsreg, smask; 4709 int framesz; 4710 int i, j; 4711 4712 l = l & 0x7f; 4713 if (use_extend) 4714 l |= extend << 16; 4715 4716 amask = (l >> 16) & 0xf; 4717 if (amask == MIPS16_ALL_ARGS) 4718 { 4719 args = 4; 4720 statics = 0; 4721 } 4722 else if (amask == MIPS16_ALL_STATICS) 4723 { 4724 args = 0; 4725 statics = 4; 4726 } 4727 else 4728 { 4729 args = amask >> 2; 4730 statics = amask & 3; 4731 } 4732 4733 if (args > 0) { 4734 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 4735 if (args > 1) 4736 (*info->fprintf_func) (info->stream, "-%s", 4737 mips_gpr_names[4 + args - 1]); 4738 need_comma = 1; 4739 } 4740 4741 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; 4742 if (framesz == 0 && !use_extend) 4743 framesz = 128; 4744 4745 (*info->fprintf_func) (info->stream, "%s%d", 4746 need_comma ? "," : "", 4747 framesz); 4748 4749 if (l & 0x40) /* $ra */ 4750 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]); 4751 4752 nsreg = (l >> 24) & 0x7; 4753 smask = 0; 4754 if (l & 0x20) /* $s0 */ 4755 smask |= 1 << 0; 4756 if (l & 0x10) /* $s1 */ 4757 smask |= 1 << 1; 4758 if (nsreg > 0) /* $s2-$s8 */ 4759 smask |= ((1 << nsreg) - 1) << 2; 4760 4761 /* Find first set static reg bit. */ 4762 for (i = 0; i < 9; i++) 4763 { 4764 if (smask & (1 << i)) 4765 { 4766 (*info->fprintf_func) (info->stream, ",%s", 4767 mips_gpr_names[i == 8 ? 30 : (16 + i)]); 4768 /* Skip over string of set bits. */ 4769 for (j = i; smask & (2 << j); j++) 4770 continue; 4771 if (j > i) 4772 (*info->fprintf_func) (info->stream, "-%s", 4773 mips_gpr_names[j == 8 ? 30 : (16 + j)]); 4774 i = j + 1; 4775 } 4776 } 4777 4778 /* Statics $ax - $a3. */ 4779 if (statics == 1) 4780 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]); 4781 else if (statics > 0) 4782 (*info->fprintf_func) (info->stream, ",%s-%s", 4783 mips_gpr_names[7 - statics + 1], 4784 mips_gpr_names[7]); 4785 } 4786 break; 4787 4788 default: 4789 /* xgettext:c-format */ 4790 (*info->fprintf_func) 4791 (info->stream, 4792 _("# internal disassembler error, unrecognised modifier (%c)"), 4793 type); 4794 abort (); 4795 } 4796 } 4797 4798 void 4799 print_mips_disassembler_options (FILE *stream) 4800 { 4801 unsigned int i; 4802 4803 fprintf (stream, _("\n\ 4804 The following MIPS specific disassembler options are supported for use\n\ 4805 with the -M switch (multiple options should be separated by commas):\n")); 4806 4807 fprintf (stream, _("\n\ 4808 gpr-names=ABI Print GPR names according to specified ABI.\n\ 4809 Default: based on binary being disassembled.\n")); 4810 4811 fprintf (stream, _("\n\ 4812 fpr-names=ABI Print FPR names according to specified ABI.\n\ 4813 Default: numeric.\n")); 4814 4815 fprintf (stream, _("\n\ 4816 cp0-names=ARCH Print CP0 register names according to\n\ 4817 specified architecture.\n\ 4818 Default: based on binary being disassembled.\n")); 4819 4820 fprintf (stream, _("\n\ 4821 hwr-names=ARCH Print HWR names according to specified \n\ 4822 architecture.\n\ 4823 Default: based on binary being disassembled.\n")); 4824 4825 fprintf (stream, _("\n\ 4826 reg-names=ABI Print GPR and FPR names according to\n\ 4827 specified ABI.\n")); 4828 4829 fprintf (stream, _("\n\ 4830 reg-names=ARCH Print CP0 register and HWR names according to\n\ 4831 specified architecture.\n")); 4832 4833 fprintf (stream, _("\n\ 4834 For the options above, the following values are supported for \"ABI\":\n\ 4835 ")); 4836 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) 4837 fprintf (stream, " %s", mips_abi_choices[i].name); 4838 fprintf (stream, _("\n")); 4839 4840 fprintf (stream, _("\n\ 4841 For the options above, The following values are supported for \"ARCH\":\n\ 4842 ")); 4843 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) 4844 if (*mips_arch_choices[i].name != '\0') 4845 fprintf (stream, " %s", mips_arch_choices[i].name); 4846 fprintf (stream, _("\n")); 4847 4848 fprintf (stream, _("\n")); 4849 } 4850 #endif 4851
