1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* 26 * DEF(name, oargs, iargs, cargs, flags) 27 */ 28 29 /* predefined ops */ 30 DEF(end, 0, 0, 0, 0) /* must be kept first */ 31 DEF(nop, 0, 0, 0, 0) 32 DEF(nop1, 0, 0, 1, 0) 33 DEF(nop2, 0, 0, 2, 0) 34 DEF(nop3, 0, 0, 3, 0) 35 DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */ 36 37 DEF(discard, 1, 0, 0, 0) 38 39 DEF(set_label, 0, 0, 1, 0) 40 DEF(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */ 41 DEF(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 42 DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 43 44 DEF(mov_i32, 1, 1, 0, 0) 45 DEF(movi_i32, 1, 0, 1, 0) 46 DEF(setcond_i32, 1, 2, 1, 0) 47 /* load/store */ 48 DEF(ld8u_i32, 1, 1, 1, 0) 49 DEF(ld8s_i32, 1, 1, 1, 0) 50 DEF(ld16u_i32, 1, 1, 1, 0) 51 DEF(ld16s_i32, 1, 1, 1, 0) 52 DEF(ld_i32, 1, 1, 1, 0) 53 DEF(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 54 DEF(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 55 DEF(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 56 /* arith */ 57 DEF(add_i32, 1, 2, 0, 0) 58 DEF(sub_i32, 1, 2, 0, 0) 59 DEF(mul_i32, 1, 2, 0, 0) 60 #ifdef TCG_TARGET_HAS_div_i32 61 DEF(div_i32, 1, 2, 0, 0) 62 DEF(divu_i32, 1, 2, 0, 0) 63 DEF(rem_i32, 1, 2, 0, 0) 64 DEF(remu_i32, 1, 2, 0, 0) 65 #endif 66 #ifdef TCG_TARGET_HAS_div2_i32 67 DEF(div2_i32, 2, 3, 0, 0) 68 DEF(divu2_i32, 2, 3, 0, 0) 69 #endif 70 DEF(and_i32, 1, 2, 0, 0) 71 DEF(or_i32, 1, 2, 0, 0) 72 DEF(xor_i32, 1, 2, 0, 0) 73 /* shifts/rotates */ 74 DEF(shl_i32, 1, 2, 0, 0) 75 DEF(shr_i32, 1, 2, 0, 0) 76 DEF(sar_i32, 1, 2, 0, 0) 77 #ifdef TCG_TARGET_HAS_rot_i32 78 DEF(rotl_i32, 1, 2, 0, 0) 79 DEF(rotr_i32, 1, 2, 0, 0) 80 #endif 81 #ifdef TCG_TARGET_HAS_deposit_i32 82 DEF(deposit_i32, 1, 2, 2, 0) 83 #endif 84 85 DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 86 #if TCG_TARGET_REG_BITS == 32 87 DEF(add2_i32, 2, 4, 0, 0) 88 DEF(sub2_i32, 2, 4, 0, 0) 89 DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 90 DEF(mulu2_i32, 2, 2, 0, 0) 91 DEF(setcond2_i32, 1, 4, 1, 0) 92 #endif 93 #ifdef TCG_TARGET_HAS_ext8s_i32 94 DEF(ext8s_i32, 1, 1, 0, 0) 95 #endif 96 #ifdef TCG_TARGET_HAS_ext16s_i32 97 DEF(ext16s_i32, 1, 1, 0, 0) 98 #endif 99 #ifdef TCG_TARGET_HAS_ext8u_i32 100 DEF(ext8u_i32, 1, 1, 0, 0) 101 #endif 102 #ifdef TCG_TARGET_HAS_ext16u_i32 103 DEF(ext16u_i32, 1, 1, 0, 0) 104 #endif 105 #ifdef TCG_TARGET_HAS_bswap16_i32 106 DEF(bswap16_i32, 1, 1, 0, 0) 107 #endif 108 #ifdef TCG_TARGET_HAS_bswap32_i32 109 DEF(bswap32_i32, 1, 1, 0, 0) 110 #endif 111 #ifdef TCG_TARGET_HAS_not_i32 112 DEF(not_i32, 1, 1, 0, 0) 113 #endif 114 #ifdef TCG_TARGET_HAS_neg_i32 115 DEF(neg_i32, 1, 1, 0, 0) 116 #endif 117 #ifdef TCG_TARGET_HAS_andc_i32 118 DEF(andc_i32, 1, 2, 0, 0) 119 #endif 120 #ifdef TCG_TARGET_HAS_orc_i32 121 DEF(orc_i32, 1, 2, 0, 0) 122 #endif 123 #ifdef TCG_TARGET_HAS_eqv_i32 124 DEF(eqv_i32, 1, 2, 0, 0) 125 #endif 126 #ifdef TCG_TARGET_HAS_nand_i32 127 DEF(nand_i32, 1, 2, 0, 0) 128 #endif 129 #ifdef TCG_TARGET_HAS_nor_i32 130 DEF(nor_i32, 1, 2, 0, 0) 131 #endif 132 133 #if TCG_TARGET_REG_BITS == 64 134 DEF(mov_i64, 1, 1, 0, 0) 135 DEF(movi_i64, 1, 0, 1, 0) 136 DEF(setcond_i64, 1, 2, 1, 0) 137 /* load/store */ 138 DEF(ld8u_i64, 1, 1, 1, 0) 139 DEF(ld8s_i64, 1, 1, 1, 0) 140 DEF(ld16u_i64, 1, 1, 1, 0) 141 DEF(ld16s_i64, 1, 1, 1, 0) 142 DEF(ld32u_i64, 1, 1, 1, 0) 143 DEF(ld32s_i64, 1, 1, 1, 0) 144 DEF(ld_i64, 1, 1, 1, 0) 145 DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 146 DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 147 DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 148 DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 149 /* arith */ 150 DEF(add_i64, 1, 2, 0, 0) 151 DEF(sub_i64, 1, 2, 0, 0) 152 DEF(mul_i64, 1, 2, 0, 0) 153 #ifdef TCG_TARGET_HAS_div_i64 154 DEF(div_i64, 1, 2, 0, 0) 155 DEF(divu_i64, 1, 2, 0, 0) 156 DEF(rem_i64, 1, 2, 0, 0) 157 DEF(remu_i64, 1, 2, 0, 0) 158 #endif 159 #ifdef TCG_TARGET_HAS_div2_i64 160 DEF(div2_i64, 2, 3, 0, 0) 161 DEF(divu2_i64, 2, 3, 0, 0) 162 #endif 163 DEF(and_i64, 1, 2, 0, 0) 164 DEF(or_i64, 1, 2, 0, 0) 165 DEF(xor_i64, 1, 2, 0, 0) 166 /* shifts/rotates */ 167 DEF(shl_i64, 1, 2, 0, 0) 168 DEF(shr_i64, 1, 2, 0, 0) 169 DEF(sar_i64, 1, 2, 0, 0) 170 #ifdef TCG_TARGET_HAS_rot_i64 171 DEF(rotl_i64, 1, 2, 0, 0) 172 DEF(rotr_i64, 1, 2, 0, 0) 173 #endif 174 #ifdef TCG_TARGET_HAS_deposit_i64 175 DEF(deposit_i64, 1, 2, 2, 0) 176 #endif 177 178 DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 179 #ifdef TCG_TARGET_HAS_ext8s_i64 180 DEF(ext8s_i64, 1, 1, 0, 0) 181 #endif 182 #ifdef TCG_TARGET_HAS_ext16s_i64 183 DEF(ext16s_i64, 1, 1, 0, 0) 184 #endif 185 #ifdef TCG_TARGET_HAS_ext32s_i64 186 DEF(ext32s_i64, 1, 1, 0, 0) 187 #endif 188 #ifdef TCG_TARGET_HAS_ext8u_i64 189 DEF(ext8u_i64, 1, 1, 0, 0) 190 #endif 191 #ifdef TCG_TARGET_HAS_ext16u_i64 192 DEF(ext16u_i64, 1, 1, 0, 0) 193 #endif 194 #ifdef TCG_TARGET_HAS_ext32u_i64 195 DEF(ext32u_i64, 1, 1, 0, 0) 196 #endif 197 #ifdef TCG_TARGET_HAS_bswap16_i64 198 DEF(bswap16_i64, 1, 1, 0, 0) 199 #endif 200 #ifdef TCG_TARGET_HAS_bswap32_i64 201 DEF(bswap32_i64, 1, 1, 0, 0) 202 #endif 203 #ifdef TCG_TARGET_HAS_bswap64_i64 204 DEF(bswap64_i64, 1, 1, 0, 0) 205 #endif 206 #ifdef TCG_TARGET_HAS_not_i64 207 DEF(not_i64, 1, 1, 0, 0) 208 #endif 209 #ifdef TCG_TARGET_HAS_neg_i64 210 DEF(neg_i64, 1, 1, 0, 0) 211 #endif 212 #ifdef TCG_TARGET_HAS_andc_i64 213 DEF(andc_i64, 1, 2, 0, 0) 214 #endif 215 #ifdef TCG_TARGET_HAS_orc_i64 216 DEF(orc_i64, 1, 2, 0, 0) 217 #endif 218 #ifdef TCG_TARGET_HAS_eqv_i64 219 DEF(eqv_i64, 1, 2, 0, 0) 220 #endif 221 #ifdef TCG_TARGET_HAS_nand_i64 222 DEF(nand_i64, 1, 2, 0, 0) 223 #endif 224 #ifdef TCG_TARGET_HAS_nor_i64 225 DEF(nor_i64, 1, 2, 0, 0) 226 #endif 227 #endif 228 229 /* QEMU specific */ 230 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 231 DEF(debug_insn_start, 0, 0, 2, 0) 232 #else 233 DEF(debug_insn_start, 0, 0, 1, 0) 234 #endif 235 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 236 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 237 /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op 238 constants must be defined */ 239 #if TCG_TARGET_REG_BITS == 32 240 #if TARGET_LONG_BITS == 32 241 DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 242 #else 243 DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 244 #endif 245 #if TARGET_LONG_BITS == 32 246 DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 247 #else 248 DEF(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 249 #endif 250 #if TARGET_LONG_BITS == 32 251 DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 252 #else 253 DEF(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 254 #endif 255 #if TARGET_LONG_BITS == 32 256 DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 257 #else 258 DEF(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 259 #endif 260 #if TARGET_LONG_BITS == 32 261 DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 262 #else 263 DEF(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 264 #endif 265 #if TARGET_LONG_BITS == 32 266 DEF(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 267 #else 268 DEF(qemu_ld32s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 269 #endif 270 #if TARGET_LONG_BITS == 32 271 DEF(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 272 #else 273 DEF(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 274 #endif 275 276 #if TARGET_LONG_BITS == 32 277 DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 278 #else 279 DEF(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 280 #endif 281 #if TARGET_LONG_BITS == 32 282 DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 283 #else 284 DEF(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 285 #endif 286 #if TARGET_LONG_BITS == 32 287 DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 288 #else 289 DEF(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 290 #endif 291 #if TARGET_LONG_BITS == 32 292 DEF(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 293 #else 294 DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 295 #endif 296 297 #else /* TCG_TARGET_REG_BITS == 32 */ 298 299 DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 300 DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 301 DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 302 DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 303 DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 304 DEF(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 305 DEF(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 306 DEF(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 307 308 DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 309 DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 310 DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 311 DEF(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 312 313 #endif /* TCG_TARGET_REG_BITS != 32 */ 314 315 #undef DEF 316
