1 /* include/linux/msm_mdp.h 2 * 3 * Copyright (C) 2007 Google Incorporated 4 * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 #ifndef _MSM_MDP_H_ 16 #define _MSM_MDP_H_ 17 18 #include <linux/types.h> 19 #include <linux/fb.h> 20 21 #define MSMFB_IOCTL_MAGIC 'm' 22 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 23 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 24 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 25 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 26 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 27 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 28 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 29 /* new ioctls's for set/get ccs matrix */ 30 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 31 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 32 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ 33 struct mdp_overlay) 34 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 35 36 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ 37 struct msmfb_overlay_data) 38 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 39 40 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ 41 struct mdp_page_protection) 42 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ 43 struct mdp_page_protection) 44 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ 45 struct mdp_overlay) 46 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 47 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ 48 struct msmfb_overlay_blt) 49 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 50 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ 51 struct mdp_histogram_start_req) 52 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 53 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 54 55 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ 56 struct msmfb_overlay_3d) 57 58 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ 59 struct msmfb_mixer_info_req) 60 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ 61 struct msmfb_overlay_data) 62 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 63 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 64 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 65 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ 66 struct msmfb_data) 67 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ 68 struct msmfb_data) 69 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 70 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 71 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 72 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 73 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 74 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 75 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ 76 struct mdp_display_commit) 77 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 78 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 79 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ 80 unsigned int) 81 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 82 83 #define FB_TYPE_3D_PANEL 0x10101010 84 #define MDP_IMGTYPE2_START 0x10000 85 #define MSMFB_DRIVER_VERSION 0xF9E8D701 86 87 enum { 88 NOTIFY_UPDATE_START, 89 NOTIFY_UPDATE_STOP, 90 NOTIFY_UPDATE_POWER_OFF, 91 }; 92 93 enum { 94 NOTIFY_TYPE_NO_UPDATE, 95 NOTIFY_TYPE_SUSPEND, 96 NOTIFY_TYPE_UPDATE, 97 }; 98 99 enum { 100 MDP_RGB_565, /* RGB 565 planer */ 101 MDP_XRGB_8888, /* RGB 888 padded */ 102 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ 103 MDP_Y_CBCR_H2V2_ADRENO, 104 MDP_ARGB_8888, /* ARGB 888 */ 105 MDP_RGB_888, /* RGB 888 planer */ 106 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ 107 MDP_YCRYCB_H2V1, /* YCrYCb interleave */ 108 MDP_CBYCRY_H2V1, /* CbYCrY interleave */ 109 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 110 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 111 MDP_Y_CRCB_H1V2, 112 MDP_Y_CBCR_H1V2, 113 MDP_RGBA_8888, /* ARGB 888 */ 114 MDP_BGRA_8888, /* ABGR 888 */ 115 MDP_RGBX_8888, /* RGBX 888 */ 116 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ 117 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ 118 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ 119 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ 120 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ 121 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 122 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ 123 MDP_YCRCB_H1V1, /* YCrCb interleave */ 124 MDP_YCBCR_H1V1, /* YCbCr interleave */ 125 MDP_BGR_565, /* BGR 565 planer */ 126 MDP_BGR_888, /* BGR 888 */ 127 MDP_Y_CBCR_H2V2_VENUS, 128 MDP_BGRX_8888, /* BGRX 8888 */ 129 MDP_YCBYCR_H2V1, /* YCbYCr interleave */ 130 MDP_IMGTYPE_LIMIT, 131 MDP_RGB_BORDERFILL, /* border fill pipe */ 132 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ 133 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ 134 }; 135 136 enum { 137 PMEM_IMG, 138 FB_IMG, 139 }; 140 141 enum { 142 HSIC_HUE = 0, 143 HSIC_SAT, 144 HSIC_INT, 145 HSIC_CON, 146 NUM_HSIC_PARAM, 147 }; 148 149 #define MDSS_MDP_ROT_ONLY 0x80 150 #define MDSS_MDP_RIGHT_MIXER 0x100 151 #define MDSS_MDP_DUAL_PIPE 0x200 152 153 /* mdp_blit_req flag values */ 154 #define MDP_ROT_NOP 0 155 #define MDP_FLIP_LR 0x1 156 #define MDP_FLIP_UD 0x2 157 #define MDP_ROT_90 0x4 158 #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) 159 #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) 160 #define MDP_DITHER 0x8 161 #define MDP_BLUR 0x10 162 #define MDP_BLEND_FG_PREMULT 0x20000 163 #define MDP_IS_FG 0x40000 164 #define MDP_DEINTERLACE 0x80000000 165 #define MDP_SHARPENING 0x40000000 166 #define MDP_NO_DMA_BARRIER_START 0x20000000 167 #define MDP_NO_DMA_BARRIER_END 0x10000000 168 #define MDP_NO_BLIT 0x08000000 169 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 170 #define MDP_BLIT_WITH_NO_DMA_BARRIERS \ 171 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 172 #define MDP_BLIT_SRC_GEM 0x04000000 173 #define MDP_BLIT_DST_GEM 0x02000000 174 #define MDP_BLIT_NON_CACHED 0x01000000 175 #define MDP_OV_PIPE_SHARE 0x00800000 176 #define MDP_DEINTERLACE_ODD 0x00400000 177 #define MDP_OV_PLAY_NOWAIT 0x00200000 178 #define MDP_SOURCE_ROTATED_90 0x00100000 179 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 180 #define MDP_BACKEND_COMPOSITION 0x00040000 181 #define MDP_BORDERFILL_SUPPORTED 0x00010000 182 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 183 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 184 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 185 #define MDP_BWC_EN 0x00000400 186 #define MDP_DECIMATION_EN 0x00000800 187 #define MDP_TRANSP_NOP 0xffffffff 188 #define MDP_ALPHA_NOP 0xff 189 190 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 191 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 192 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 193 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 194 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 195 /* Sentinel: Don't use! */ 196 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 197 /* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ 198 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 199 200 struct mdp_rect { 201 uint32_t x; 202 uint32_t y; 203 uint32_t w; 204 uint32_t h; 205 }; 206 207 struct mdp_img { 208 uint32_t width; 209 uint32_t height; 210 uint32_t format; 211 uint32_t offset; 212 int memory_id; /* the file descriptor */ 213 uint32_t priv; 214 }; 215 216 /* 217 * {3x3} + {3} ccs matrix 218 */ 219 220 #define MDP_CCS_RGB2YUV 0 221 #define MDP_CCS_YUV2RGB 1 222 223 #define MDP_CCS_SIZE 9 224 #define MDP_BV_SIZE 3 225 226 struct mdp_ccs { 227 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ 228 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ 229 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ 230 }; 231 232 struct mdp_csc { 233 int id; 234 uint32_t csc_mv[9]; 235 uint32_t csc_pre_bv[3]; 236 uint32_t csc_post_bv[3]; 237 uint32_t csc_pre_lv[6]; 238 uint32_t csc_post_lv[6]; 239 }; 240 241 /* The version of the mdp_blit_req structure so that 242 * user applications can selectively decide which functionality 243 * to include 244 */ 245 246 #define MDP_BLIT_REQ_VERSION 2 247 248 struct mdp_blit_req { 249 struct mdp_img src; 250 struct mdp_img dst; 251 struct mdp_rect src_rect; 252 struct mdp_rect dst_rect; 253 uint32_t alpha; 254 uint32_t transp_mask; 255 uint32_t flags; 256 int sharpening_strength; /* -127 <--> 127, default 64 */ 257 }; 258 259 struct mdp_blit_req_list { 260 uint32_t count; 261 struct mdp_blit_req req[]; 262 }; 263 264 #define MSMFB_DATA_VERSION 2 265 266 struct msmfb_data { 267 uint32_t offset; 268 int memory_id; 269 int id; 270 uint32_t flags; 271 uint32_t priv; 272 uint32_t iova; 273 }; 274 275 #define MSMFB_NEW_REQUEST -1 276 277 struct msmfb_overlay_data { 278 uint32_t id; 279 struct msmfb_data data; 280 uint32_t version_key; 281 struct msmfb_data plane1_data; 282 struct msmfb_data plane2_data; 283 struct msmfb_data dst_data; 284 }; 285 286 struct msmfb_img { 287 uint32_t width; 288 uint32_t height; 289 uint32_t format; 290 }; 291 292 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 293 struct msmfb_writeback_data { 294 struct msmfb_data buf_info; 295 struct msmfb_img img; 296 }; 297 298 #define MDP_PP_OPS_ENABLE 0x1 299 #define MDP_PP_OPS_READ 0x2 300 #define MDP_PP_OPS_WRITE 0x4 301 #define MDP_PP_OPS_DISABLE 0x8 302 #define MDP_PP_IGC_FLAG_ROM0 0x10 303 #define MDP_PP_IGC_FLAG_ROM1 0x20 304 305 #define MDSS_PP_DSPP_CFG 0x000 306 #define MDSS_PP_SSPP_CFG 0x100 307 #define MDSS_PP_LM_CFG 0x200 308 #define MDSS_PP_WB_CFG 0x300 309 310 #define MDSS_PP_ARG_MASK 0x3C00 311 #define MDSS_PP_ARG_NUM 4 312 #define MDSS_PP_ARG_SHIFT 10 313 #define MDSS_PP_LOCATION_MASK 0x0300 314 #define MDSS_PP_LOGICAL_MASK 0x00FF 315 316 #define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 317 #define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 318 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 319 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 320 321 322 struct mdp_qseed_cfg { 323 uint32_t table_num; 324 uint32_t ops; 325 uint32_t len; 326 uint32_t *data; 327 }; 328 329 struct mdp_sharp_cfg { 330 uint32_t flags; 331 uint32_t strength; 332 uint32_t edge_thr; 333 uint32_t smooth_thr; 334 uint32_t noise_thr; 335 }; 336 337 struct mdp_qseed_cfg_data { 338 uint32_t block; 339 struct mdp_qseed_cfg qseed_data; 340 }; 341 342 #define MDP_OVERLAY_PP_CSC_CFG 0x1 343 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 344 #define MDP_OVERLAY_PP_PA_CFG 0x4 345 #define MDP_OVERLAY_PP_IGC_CFG 0x8 346 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 347 #define MDP_OVERLAY_PP_HIST_CFG 0x20 348 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 349 350 #define MDP_CSC_FLAG_ENABLE 0x1 351 #define MDP_CSC_FLAG_YUV_IN 0x2 352 #define MDP_CSC_FLAG_YUV_OUT 0x4 353 354 struct mdp_csc_cfg { 355 /* flags for enable CSC, toggling RGB,YUV input/output */ 356 uint32_t flags; 357 uint32_t csc_mv[9]; 358 uint32_t csc_pre_bv[3]; 359 uint32_t csc_post_bv[3]; 360 uint32_t csc_pre_lv[6]; 361 uint32_t csc_post_lv[6]; 362 }; 363 364 struct mdp_csc_cfg_data { 365 uint32_t block; 366 struct mdp_csc_cfg csc_data; 367 }; 368 369 struct mdp_pa_cfg { 370 uint32_t flags; 371 uint32_t hue_adj; 372 uint32_t sat_adj; 373 uint32_t val_adj; 374 uint32_t cont_adj; 375 }; 376 377 struct mdp_igc_lut_data { 378 uint32_t block; 379 uint32_t len, ops; 380 uint32_t *c0_c1_data; 381 uint32_t *c2_data; 382 }; 383 384 struct mdp_histogram_cfg { 385 uint32_t ops; 386 uint32_t block; 387 uint8_t frame_cnt; 388 uint8_t bit_mask; 389 uint16_t num_bins; 390 }; 391 392 struct mdp_hist_lut_data { 393 uint32_t block; 394 uint32_t ops; 395 uint32_t len; 396 uint32_t *data; 397 }; 398 399 struct mdp_overlay_pp_params { 400 uint32_t config_ops; 401 struct mdp_csc_cfg csc_cfg; 402 struct mdp_qseed_cfg qseed_cfg[2]; 403 struct mdp_pa_cfg pa_cfg; 404 struct mdp_igc_lut_data igc_cfg; 405 struct mdp_sharp_cfg sharp_cfg; 406 struct mdp_histogram_cfg hist_cfg; 407 struct mdp_hist_lut_data hist_lut_cfg; 408 }; 409 410 /** 411 * enum mdss_mdp_blend_op - Different blend operations set by userspace 412 * 413 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 414 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 415 * would appear opaque in case fg plane alpha is 416 * 0xff. 417 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has 418 * alpha pre-multiplication done. If fg plane alpha 419 * is less than 0xff, apply modulation as well. This 420 * operation is intended on layers having alpha 421 * channel. 422 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha 423 * pre-multiplied. Apply pre-multiplication. If fg 424 * plane alpha is less than 0xff, apply modulation as 425 * well. 426 * @BLEND_OP_MAX: Used to track maximum blend operation possible by 427 * mdp. 428 */ 429 enum mdss_mdp_blend_op { 430 BLEND_OP_NOT_DEFINED = 0, 431 BLEND_OP_OPAQUE, 432 BLEND_OP_PREMULTIPLIED, 433 BLEND_OP_COVERAGE, 434 BLEND_OP_MAX, 435 }; 436 437 struct mdp_overlay { 438 struct msmfb_img src; 439 struct mdp_rect src_rect; 440 struct mdp_rect dst_rect; 441 uint32_t z_order; /* stage number */ 442 uint32_t is_fg; /* control alpha & transp */ 443 uint32_t alpha; 444 uint32_t blend_op; 445 uint32_t transp_mask; 446 uint32_t flags; 447 uint32_t id; 448 uint32_t user_data[7]; 449 uint8_t horz_deci; 450 uint8_t vert_deci; 451 struct mdp_overlay_pp_params overlay_pp_cfg; 452 }; 453 454 struct msmfb_overlay_3d { 455 uint32_t is_3d; 456 uint32_t width; 457 uint32_t height; 458 }; 459 460 461 struct msmfb_overlay_blt { 462 uint32_t enable; 463 uint32_t offset; 464 uint32_t width; 465 uint32_t height; 466 uint32_t bpp; 467 }; 468 469 struct mdp_histogram { 470 uint32_t frame_cnt; 471 uint32_t bin_cnt; 472 uint32_t *r; 473 uint32_t *g; 474 uint32_t *b; 475 }; 476 477 enum { 478 DISPLAY_MISR_EDP, 479 DISPLAY_MISR_DSI0, 480 DISPLAY_MISR_DSI1, 481 DISPLAY_MISR_HDMI, 482 DISPLAY_MISR_LCDC, 483 DISPLAY_MISR_ATV, 484 DISPLAY_MISR_DSI_CMD, 485 DISPLAY_MISR_MAX 486 }; 487 488 enum { 489 MISR_OP_NONE, 490 MISR_OP_SFM, 491 MISR_OP_MFM, 492 MISR_OP_BM, 493 MISR_OP_MAX 494 }; 495 496 struct mdp_misr { 497 uint32_t block_id; 498 uint32_t frame_count; 499 uint32_t crc_op_mode; 500 uint32_t crc_value[32]; 501 }; 502 503 /* 504 505 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up 506 507 MDP_BLOCK_RESERVED is provided for backward compatibility and is 508 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used 509 instead. 510 511 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, 512 same for others. 513 514 */ 515 516 enum { 517 MDP_BLOCK_RESERVED = 0, 518 MDP_BLOCK_OVERLAY_0, 519 MDP_BLOCK_OVERLAY_1, 520 MDP_BLOCK_VG_1, 521 MDP_BLOCK_VG_2, 522 MDP_BLOCK_RGB_1, 523 MDP_BLOCK_RGB_2, 524 MDP_BLOCK_DMA_P, 525 MDP_BLOCK_DMA_S, 526 MDP_BLOCK_DMA_E, 527 MDP_BLOCK_OVERLAY_2, 528 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 529 MDP_LOGICAL_BLOCK_DISP_1, 530 MDP_LOGICAL_BLOCK_DISP_2, 531 MDP_BLOCK_MAX, 532 }; 533 534 /* 535 * mdp_histogram_start_req is used to provide the parameters for 536 * histogram start request 537 */ 538 539 struct mdp_histogram_start_req { 540 uint32_t block; 541 uint8_t frame_cnt; 542 uint8_t bit_mask; 543 uint16_t num_bins; 544 }; 545 546 /* 547 * mdp_histogram_data is used to return the histogram data, once 548 * the histogram is done/stopped/cance 549 */ 550 551 struct mdp_histogram_data { 552 uint32_t block; 553 uint32_t bin_cnt; 554 uint32_t *c0; 555 uint32_t *c1; 556 uint32_t *c2; 557 uint32_t *extra_info; 558 }; 559 560 struct mdp_pcc_coeff { 561 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 562 }; 563 564 struct mdp_pcc_cfg_data { 565 uint32_t block; 566 uint32_t ops; 567 struct mdp_pcc_coeff r, g, b; 568 }; 569 570 #define MDP_GAMUT_TABLE_NUM 8 571 572 enum { 573 mdp_lut_igc, 574 mdp_lut_pgc, 575 mdp_lut_hist, 576 mdp_lut_max, 577 }; 578 579 struct mdp_ar_gc_lut_data { 580 uint32_t x_start; 581 uint32_t slope; 582 uint32_t offset; 583 }; 584 585 struct mdp_pgc_lut_data { 586 uint32_t block; 587 uint32_t flags; 588 uint8_t num_r_stages; 589 uint8_t num_g_stages; 590 uint8_t num_b_stages; 591 struct mdp_ar_gc_lut_data *r_data; 592 struct mdp_ar_gc_lut_data *g_data; 593 struct mdp_ar_gc_lut_data *b_data; 594 }; 595 596 597 struct mdp_lut_cfg_data { 598 uint32_t lut_type; 599 union { 600 struct mdp_igc_lut_data igc_lut_data; 601 struct mdp_pgc_lut_data pgc_lut_data; 602 struct mdp_hist_lut_data hist_lut_data; 603 } data; 604 }; 605 606 struct mdp_bl_scale_data { 607 uint32_t min_lvl; 608 uint32_t scale; 609 }; 610 611 struct mdp_pa_cfg_data { 612 uint32_t block; 613 struct mdp_pa_cfg pa_data; 614 }; 615 616 struct mdp_dither_cfg_data { 617 uint32_t block; 618 uint32_t flags; 619 uint32_t g_y_depth; 620 uint32_t r_cr_depth; 621 uint32_t b_cb_depth; 622 }; 623 624 struct mdp_gamut_cfg_data { 625 uint32_t block; 626 uint32_t flags; 627 uint32_t gamut_first; 628 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 629 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; 630 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; 631 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; 632 }; 633 634 struct mdp_calib_config_data { 635 uint32_t ops; 636 uint32_t addr; 637 uint32_t data; 638 }; 639 640 struct mdp_calib_config_buffer { 641 uint32_t ops; 642 uint32_t size; 643 uint32_t *buffer; 644 }; 645 646 struct mdp_calib_dcm_state { 647 uint32_t ops; 648 uint32_t dcm_state; 649 }; 650 651 enum { 652 DCM_UNINIT, 653 DCM_UNBLANK, 654 DCM_ENTER, 655 DCM_EXIT, 656 DCM_BLANK, 657 }; 658 659 #define MDSS_MAX_BL_BRIGHTNESS 255 660 #define AD_BL_LIN_LEN (MDSS_MAX_BL_BRIGHTNESS + 1) 661 662 #define MDSS_AD_MODE_AUTO_BL 0x0 663 #define MDSS_AD_MODE_AUTO_STR 0x1 664 #define MDSS_AD_MODE_TARG_STR 0x3 665 #define MDSS_AD_MODE_MAN_STR 0x7 666 #define MDSS_AD_MODE_CALIB 0xF 667 668 #define MDP_PP_AD_INIT 0x10 669 #define MDP_PP_AD_CFG 0x20 670 671 struct mdss_ad_init { 672 uint32_t asym_lut[33]; 673 uint32_t color_corr_lut[33]; 674 uint8_t i_control[2]; 675 uint16_t black_lvl; 676 uint16_t white_lvl; 677 uint8_t var; 678 uint8_t limit_ampl; 679 uint8_t i_dither; 680 uint8_t slope_max; 681 uint8_t slope_min; 682 uint8_t dither_ctl; 683 uint8_t format; 684 uint8_t auto_size; 685 uint16_t frame_w; 686 uint16_t frame_h; 687 uint8_t logo_v; 688 uint8_t logo_h; 689 uint32_t bl_lin_len; 690 uint32_t *bl_lin; 691 uint32_t *bl_lin_inv; 692 }; 693 694 #define MDSS_AD_BL_CTRL_MODE_EN 1 695 #define MDSS_AD_BL_CTRL_MODE_DIS 0 696 struct mdss_ad_cfg { 697 uint32_t mode; 698 uint32_t al_calib_lut[33]; 699 uint16_t backlight_min; 700 uint16_t backlight_max; 701 uint16_t backlight_scale; 702 uint16_t amb_light_min; 703 uint16_t filter[2]; 704 uint16_t calib[4]; 705 uint8_t strength_limit; 706 uint8_t t_filter_recursion; 707 uint16_t stab_itr; 708 uint32_t bl_ctrl_mode; 709 }; 710 711 /* ops uses standard MDP_PP_* flags */ 712 struct mdss_ad_init_cfg { 713 uint32_t ops; 714 union { 715 struct mdss_ad_init init; 716 struct mdss_ad_cfg cfg; 717 } params; 718 }; 719 720 /* mode uses MDSS_AD_MODE_* flags */ 721 struct mdss_ad_input { 722 uint32_t mode; 723 union { 724 uint32_t amb_light; 725 uint32_t strength; 726 uint32_t calib_bl; 727 } in; 728 uint32_t output; 729 }; 730 731 #define MDSS_CALIB_MODE_BL 0x1 732 struct mdss_calib_cfg { 733 uint32_t ops; 734 uint32_t calib_mask; 735 }; 736 737 enum { 738 mdp_op_pcc_cfg, 739 mdp_op_csc_cfg, 740 mdp_op_lut_cfg, 741 mdp_op_qseed_cfg, 742 mdp_bl_scale_cfg, 743 mdp_op_pa_cfg, 744 mdp_op_dither_cfg, 745 mdp_op_gamut_cfg, 746 mdp_op_calib_cfg, 747 mdp_op_ad_cfg, 748 mdp_op_ad_input, 749 mdp_op_calib_mode, 750 mdp_op_calib_buffer, 751 mdp_op_calib_dcm_state, 752 mdp_op_max, 753 }; 754 755 enum { 756 WB_FORMAT_NV12, 757 WB_FORMAT_RGB_565, 758 WB_FORMAT_RGB_888, 759 WB_FORMAT_xRGB_8888, 760 WB_FORMAT_ARGB_8888, 761 WB_FORMAT_BGRA_8888, 762 WB_FORMAT_BGRX_8888, 763 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ 764 }; 765 766 struct msmfb_mdp_pp { 767 uint32_t op; 768 union { 769 struct mdp_pcc_cfg_data pcc_cfg_data; 770 struct mdp_csc_cfg_data csc_cfg_data; 771 struct mdp_lut_cfg_data lut_cfg_data; 772 struct mdp_qseed_cfg_data qseed_cfg_data; 773 struct mdp_bl_scale_data bl_scale_data; 774 struct mdp_pa_cfg_data pa_cfg_data; 775 struct mdp_dither_cfg_data dither_cfg_data; 776 struct mdp_gamut_cfg_data gamut_cfg_data; 777 struct mdp_calib_config_data calib_cfg; 778 struct mdss_ad_init_cfg ad_init_cfg; 779 struct mdss_calib_cfg mdss_calib_cfg; 780 struct mdss_ad_input ad_input; 781 struct mdp_calib_config_buffer calib_buffer; 782 struct mdp_calib_dcm_state calib_dcm; 783 } data; 784 }; 785 786 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 787 enum { 788 metadata_op_none, 789 metadata_op_base_blend, 790 metadata_op_frame_rate, 791 metadata_op_vic, 792 metadata_op_wb_format, 793 metadata_op_get_caps, 794 metadata_op_crc, 795 metadata_op_max 796 }; 797 798 struct mdp_blend_cfg { 799 uint32_t is_premultiplied; 800 }; 801 802 struct mdp_mixer_cfg { 803 uint32_t writeback_format; 804 uint32_t alpha; 805 }; 806 807 struct mdss_hw_caps { 808 uint32_t mdp_rev; 809 uint8_t rgb_pipes; 810 uint8_t vig_pipes; 811 uint8_t dma_pipes; 812 uint32_t features; 813 }; 814 815 struct msmfb_metadata { 816 uint32_t op; 817 uint32_t flags; 818 union { 819 struct mdp_misr misr_request; 820 struct mdp_blend_cfg blend_cfg; 821 struct mdp_mixer_cfg mixer_cfg; 822 uint32_t panel_frame_rate; 823 uint32_t video_info_code; 824 struct mdss_hw_caps caps; 825 } data; 826 }; 827 828 #define MDP_MAX_FENCE_FD 32 829 #define MDP_BUF_SYNC_FLAG_WAIT 1 830 831 struct mdp_buf_sync { 832 uint32_t flags; 833 uint32_t acq_fen_fd_cnt; 834 uint32_t session_id; 835 int *acq_fen_fd; 836 int *rel_fen_fd; 837 int *retire_fen_fd; 838 }; 839 840 struct mdp_async_blit_req_list { 841 struct mdp_buf_sync sync; 842 uint32_t count; 843 struct mdp_blit_req req[]; 844 }; 845 846 #define MDP_DISPLAY_COMMIT_OVERLAY 1 847 848 struct mdp_display_commit { 849 uint32_t flags; 850 uint32_t wait_for_finish; 851 struct fb_var_screeninfo var; 852 }; 853 854 struct mdp_page_protection { 855 uint32_t page_protection; 856 }; 857 858 859 struct mdp_mixer_info { 860 int pndx; 861 int pnum; 862 int ptype; 863 int mixer_num; 864 int z_order; 865 }; 866 867 #define MAX_PIPE_PER_MIXER 4 868 869 struct msmfb_mixer_info_req { 870 int mixer_num; 871 int cnt; 872 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 873 }; 874 875 enum { 876 DISPLAY_SUBSYSTEM_ID, 877 ROTATOR_SUBSYSTEM_ID, 878 }; 879 880 enum { 881 MDP_IOMMU_DOMAIN_CP, 882 MDP_IOMMU_DOMAIN_NS, 883 }; 884 885 enum { 886 MDP_WRITEBACK_MIRROR_OFF, 887 MDP_WRITEBACK_MIRROR_ON, 888 MDP_WRITEBACK_MIRROR_PAUSE, 889 MDP_WRITEBACK_MIRROR_RESUME, 890 }; 891 892 #ifdef __KERNEL__ 893 int msm_fb_get_iommu_domain(struct fb_info *info, int domain); 894 /* get the framebuffer physical address information */ 895 int get_fb_phys_info(unsigned long *start, unsigned long *len, int fb_num, 896 int subsys_id); 897 struct fb_info *msm_fb_get_writeback_fb(void); 898 int msm_fb_writeback_init(struct fb_info *info); 899 int msm_fb_writeback_start(struct fb_info *info); 900 int msm_fb_writeback_queue_buffer(struct fb_info *info, 901 struct msmfb_data *data); 902 int msm_fb_writeback_dequeue_buffer(struct fb_info *info, 903 struct msmfb_data *data); 904 int msm_fb_writeback_stop(struct fb_info *info); 905 int msm_fb_writeback_terminate(struct fb_info *info); 906 int msm_fb_writeback_set_secure(struct fb_info *info, int enable); 907 #endif 908 909 #endif /*_MSM_MDP_H_*/ 910
