1 /* Instruction printing code for the ARM 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 3 Free Software Foundation, Inc. 4 Contributed by Richard Earnshaw (rwe (at) pegasus.esprit.ec.org) 5 Modification by James G. Smith (jsmith (at) cygnus.co.uk) 6 7 This file is part of libopcodes. 8 9 This program is free software; you can redistribute it and/or modify it under 10 the terms of the GNU General Public License as published by the Free 11 Software Foundation; either version 2 of the License, or (at your option) 12 any later version. 13 14 This program is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 22 23 /* Modified to fit into the qtools framework. The main differences are: 24 * 25 * - The disassembly function returns a string instead of writing it to a 26 * file stream. 27 * 28 * - All the references to the struct "disassemble_info" have been removed. 29 * 30 * - A set of enums for the thumb opcodes have been defined, along with a 31 * "decode()" function that maps a thumb instruction to an opcode enum. 32 * 33 * - Eliminated uses of the special characters ', `, and ? from the 34 * thumb_opcodes[] table so that we can easily specify separate opcodes 35 * for distinct instructions. 36 */ 37 38 #include <stdio.h> 39 #include <stdlib.h> 40 #include <string.h> 41 #include <inttypes.h> 42 #include "opcode.h" 43 44 45 struct thumb_opcode 46 { 47 unsigned short value, mask; /* recognise instruction if (op&mask)==value */ 48 Opcode opcode; 49 const char * assembler; /* how to disassemble this instruction */ 50 }; 51 52 /* format of the assembler string : 53 54 %% % 55 %<bitfield>d print the bitfield in decimal 56 %<bitfield>x print the bitfield in hex 57 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 58 %<bitfield>r print as an ARM register 59 %<bitfield>f print a floating point constant if >7 else a 60 floating point register 61 %<code>y print a single precision VFP reg. 62 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair 63 %<code>z print a double precision VFP reg 64 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list 65 %c print condition code (always bits 28-31) 66 %P print floating point precision in arithmetic insn 67 %Q print floating point precision in ldf/stf insn 68 %R print floating point rounding mode 69 %<bitnum>'c print specified char iff bit is one 70 %<bitnum>`c print specified char iff bit is zero 71 %<bitnum>?ab print a if bit is one else print b 72 %p print 'p' iff bits 12-15 are 15 73 %t print 't' iff bit 21 set and bit 24 clear 74 %o print operand2 (immediate or register + shift) 75 %a print address for ldr/str instruction 76 %s print address for ldr/str halfword/signextend instruction 77 %b print branch destination 78 %B print arm BLX(1) destination 79 %A print address for ldc/stc/ldf/stf instruction 80 %m print register mask for ldm/stm instruction 81 %C print the PSR sub type. 82 %F print the COUNT field of a LFM/SFM instruction. 83 Thumb specific format options: 84 %D print Thumb register (bits 0..2 as high number if bit 7 set) 85 %S print Thumb register (bits 3..5 as high number if bit 6 set) 86 %<bitfield>I print bitfield as a signed decimal 87 (top bit of range being the sign bit) 88 %M print Thumb register mask 89 %N print Thumb register mask (with LR) 90 %O print Thumb register mask (with PC) 91 %T print Thumb condition code (always bits 8-11) 92 %I print cirrus signed shift immediate: bits 0..3|4..6 93 %<bitfield>B print Thumb branch destination (signed displacement) 94 %<bitfield>W print (bitfield * 4) as a decimal 95 %<bitfield>H print (bitfield * 2) as a decimal 96 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol 97 */ 98 99 100 static struct thumb_opcode thumb_opcodes[] = 101 { 102 /* Thumb instructions. */ 103 104 /* ARM V5 ISA extends Thumb. */ 105 {0xbe00, 0xff00, OP_THUMB_BKPT, "bkpt\t%0-7x"}, 106 {0x4780, 0xff87, OP_THUMB_BLX, "blx\t%3-6r"}, /* note: 4 bit register number. */ 107 /* Format 5 instructions do not update the PSR. */ 108 {0x1C00, 0xFFC0, OP_THUMB_MOV, "mov\t%0-2r, %3-5r"}, 109 /* Format 4. */ 110 {0x4000, 0xFFC0, OP_THUMB_AND, "and\t%0-2r, %3-5r"}, 111 {0x4040, 0xFFC0, OP_THUMB_EOR, "eor\t%0-2r, %3-5r"}, 112 {0x4080, 0xFFC0, OP_THUMB_LSL, "lsl\t%0-2r, %3-5r"}, 113 {0x40C0, 0xFFC0, OP_THUMB_LSR, "lsr\t%0-2r, %3-5r"}, 114 {0x4100, 0xFFC0, OP_THUMB_ASR, "asr\t%0-2r, %3-5r"}, 115 {0x4140, 0xFFC0, OP_THUMB_ADC, "adc\t%0-2r, %3-5r"}, 116 {0x4180, 0xFFC0, OP_THUMB_SBC, "sbc\t%0-2r, %3-5r"}, 117 {0x41C0, 0xFFC0, OP_THUMB_ROR, "ror\t%0-2r, %3-5r"}, 118 {0x4200, 0xFFC0, OP_THUMB_TST, "tst\t%0-2r, %3-5r"}, 119 {0x4240, 0xFFC0, OP_THUMB_NEG, "neg\t%0-2r, %3-5r"}, 120 {0x4280, 0xFFC0, OP_THUMB_CMP, "cmp\t%0-2r, %3-5r"}, 121 {0x42C0, 0xFFC0, OP_THUMB_CMN, "cmn\t%0-2r, %3-5r"}, 122 {0x4300, 0xFFC0, OP_THUMB_ORR, "orr\t%0-2r, %3-5r"}, 123 {0x4340, 0xFFC0, OP_THUMB_MUL, "mul\t%0-2r, %3-5r"}, 124 {0x4380, 0xFFC0, OP_THUMB_BIC, "bic\t%0-2r, %3-5r"}, 125 {0x43C0, 0xFFC0, OP_THUMB_MVN, "mvn\t%0-2r, %3-5r"}, 126 /* format 13 */ 127 {0xB000, 0xFF80, OP_THUMB_ADD, "add\tsp, #%0-6W"}, 128 {0xB080, 0xFF80, OP_THUMB_SUB, "sub\tsp, #%0-6W"}, 129 /* format 5 */ 130 {0x4700, 0xFF80, OP_THUMB_BX, "bx\t%S"}, 131 {0x4400, 0xFF00, OP_THUMB_ADD, "add\t%D, %S"}, 132 {0x4500, 0xFF00, OP_THUMB_CMP, "cmp\t%D, %S"}, 133 {0x4600, 0xFF00, OP_THUMB_MOV, "mov\t%D, %S"}, 134 /* format 14 */ 135 {0xB400, 0xFE00, OP_THUMB_PUSH, "push\t%N"}, 136 {0xBC00, 0xFE00, OP_THUMB_POP, "pop\t%O"}, 137 /* format 2 */ 138 {0x1800, 0xFE00, OP_THUMB_ADD, "add\t%0-2r, %3-5r, %6-8r"}, 139 {0x1A00, 0xFE00, OP_THUMB_SUB, "sub\t%0-2r, %3-5r, %6-8r"}, 140 {0x1C00, 0xFE00, OP_THUMB_ADD, "add\t%0-2r, %3-5r, #%6-8d"}, 141 {0x1E00, 0xFE00, OP_THUMB_SUB, "sub\t%0-2r, %3-5r, #%6-8d"}, 142 /* format 8 */ 143 {0x5200, 0xFE00, OP_THUMB_STRH, "strh\t%0-2r, [%3-5r, %6-8r]"}, 144 {0x5A00, 0xFE00, OP_THUMB_LDRH, "ldrh\t%0-2r, [%3-5r, %6-8r]"}, 145 {0x5600, 0xFE00, OP_THUMB_LDRSB, "ldrsb\t%0-2r, [%3-5r, %6-8r]"}, 146 {0x5E00, 0xFE00, OP_THUMB_LDRSH, "ldrsh\t%0-2r, [%3-5r, %6-8r]"}, 147 /* format 7 */ 148 {0x5000, 0xFE00, OP_THUMB_STR, "str\t%0-2r, [%3-5r, %6-8r]"}, 149 {0x5400, 0xFE00, OP_THUMB_STRB, "strb\t%0-2r, [%3-5r, %6-8r]"}, 150 {0x5800, 0xFE00, OP_THUMB_LDR, "ldr\t%0-2r, [%3-5r, %6-8r]"}, 151 {0x5C00, 0xFE00, OP_THUMB_LDRB, "ldrb\t%0-2r, [%3-5r, %6-8r]"}, 152 /* format 1 */ 153 {0x0000, 0xF800, OP_THUMB_LSL, "lsl\t%0-2r, %3-5r, #%6-10d"}, 154 {0x0800, 0xF800, OP_THUMB_LSR, "lsr\t%0-2r, %3-5r, #%6-10d"}, 155 {0x1000, 0xF800, OP_THUMB_ASR, "asr\t%0-2r, %3-5r, #%6-10d"}, 156 /* format 3 */ 157 {0x2000, 0xF800, OP_THUMB_MOV, "mov\t%8-10r, #%0-7d"}, 158 {0x2800, 0xF800, OP_THUMB_CMP, "cmp\t%8-10r, #%0-7d"}, 159 {0x3000, 0xF800, OP_THUMB_ADD, "add\t%8-10r, #%0-7d"}, 160 {0x3800, 0xF800, OP_THUMB_SUB, "sub\t%8-10r, #%0-7d"}, 161 /* format 6 */ 162 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ 163 {0x4800, 0xF800, OP_THUMB_LDR, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, 164 /* format 9 */ 165 {0x6000, 0xF800, OP_THUMB_STR, "str\t%0-2r, [%3-5r, #%6-10W]"}, 166 {0x6800, 0xF800, OP_THUMB_LDR, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, 167 {0x7000, 0xF800, OP_THUMB_STRB, "strb\t%0-2r, [%3-5r, #%6-10d]"}, 168 {0x7800, 0xF800, OP_THUMB_LDRB, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, 169 /* format 10 */ 170 {0x8000, 0xF800, OP_THUMB_STRH, "strh\t%0-2r, [%3-5r, #%6-10H]"}, 171 {0x8800, 0xF800, OP_THUMB_LDRH, "ldrh\t%0-2r, [%3-5r, #%6-10H]"}, 172 /* format 11 */ 173 {0x9000, 0xF800, OP_THUMB_STR, "str\t%8-10r, [sp, #%0-7W]"}, 174 {0x9800, 0xF800, OP_THUMB_LDR, "ldr\t%8-10r, [sp, #%0-7W]"}, 175 /* format 12 */ 176 {0xA000, 0xF800, OP_THUMB_ADD, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"}, 177 {0xA800, 0xF800, OP_THUMB_ADD, "add\t%8-10r, sp, #%0-7W"}, 178 /* format 15 */ 179 {0xC000, 0xF800, OP_THUMB_STMIA, "stmia\t%8-10r!,%M"}, 180 {0xC800, 0xF800, OP_THUMB_LDMIA, "ldmia\t%8-10r!,%M"}, 181 /* format 18 */ 182 {0xE000, 0xF800, OP_THUMB_B, "b\t%0-10B"}, 183 /* format 19 */ 184 /* special processing required in disassembler */ 185 {0xF000, 0xF800, OP_THUMB_BL, ""}, 186 {0xF800, 0xF800, OP_THUMB_BL, "second half of BL instruction %0-15x"}, 187 {0xE800, 0xF800, OP_THUMB_BLX, "second half of BLX instruction %0-15x"}, 188 /* format 16 */ 189 {0xD000, 0xFF00, OP_THUMB_B, "beq\t%0-7B"}, 190 {0xD100, 0xFF00, OP_THUMB_B, "bne\t%0-7B"}, 191 {0xD200, 0xFF00, OP_THUMB_B, "bcs\t%0-7B"}, 192 {0xD300, 0xFF00, OP_THUMB_B, "bcc\t%0-7B"}, 193 {0xD400, 0xFF00, OP_THUMB_B, "bmi\t%0-7B"}, 194 {0xD500, 0xFF00, OP_THUMB_B, "bpl\t%0-7B"}, 195 {0xD600, 0xFF00, OP_THUMB_B, "bvs\t%0-7B"}, 196 {0xD700, 0xFF00, OP_THUMB_B, "bvc\t%0-7B"}, 197 {0xD800, 0xFF00, OP_THUMB_B, "bhi\t%0-7B"}, 198 {0xD900, 0xFF00, OP_THUMB_B, "bls\t%0-7B"}, 199 {0xDA00, 0xFF00, OP_THUMB_B, "bge\t%0-7B"}, 200 {0xDB00, 0xFF00, OP_THUMB_B, "blt\t%0-7B"}, 201 {0xDC00, 0xFF00, OP_THUMB_B, "bgt\t%0-7B"}, 202 {0xDD00, 0xFF00, OP_THUMB_B, "ble\t%0-7B"}, 203 /* format 17 */ 204 {0xDE00, 0xFF00, OP_THUMB_UNDEFINED, "undefined"}, 205 {0xDF00, 0xFF00, OP_THUMB_SWI, "swi\t%0-7d"}, 206 /* format 9 */ 207 {0x6000, 0xF800, OP_THUMB_STR, "str\t%0-2r, [%3-5r, #%6-10W]"}, 208 {0x6800, 0xF800, OP_THUMB_LDR, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, 209 {0x7000, 0xF800, OP_THUMB_STRB, "strb\t%0-2r, [%3-5r, #%6-10d]"}, 210 {0x7800, 0xF800, OP_THUMB_LDRB, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, 211 /* the rest */ 212 {0x0000, 0x0000, OP_THUMB_UNDEFINED, "undefined instruction %0-15x"}, 213 {0x0000, 0x0000, OP_END, 0} 214 }; 215 216 #define BDISP23(x,y) ((((((x) & 0x07ff) << 11) | ((y) & 0x07ff)) \ 217 ^ 0x200000) - 0x200000) /* 23bit */ 218 219 static const char * arm_conditional[] = 220 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 221 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"}; 222 223 typedef struct 224 { 225 const char * name; 226 const char * description; 227 const char * reg_names[16]; 228 } 229 arm_regname; 230 231 static arm_regname regnames[] = 232 { 233 { "raw" , "Select raw register names", 234 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, 235 { "gcc", "Select register names used by GCC", 236 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, 237 { "std", "Select register names used in ARM's ISA documentation", 238 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, 239 { "apcs", "Select register names used in the APCS", 240 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, 241 { "atpcs", "Select register names used in the ATPCS", 242 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 243 { "special-atpcs", "Select special register names used in the ATPCS", 244 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} 245 }; 246 247 /* Default to STD register name set. */ 248 static unsigned int regname_selected = 2; 249 250 #define NUM_ARM_REGNAMES NUM_ELEM (regnames) 251 #define arm_regnames regnames[regname_selected].reg_names 252 253 Opcode decode_insn_thumb(uint32_t given) 254 { 255 struct thumb_opcode * insn; 256 257 for (insn = thumb_opcodes; insn->assembler; insn++) { 258 if ((given & insn->mask) == insn->value) 259 return insn->opcode; 260 } 261 return OP_THUMB_UNDEFINED; 262 } 263 264 // Generates the disassembly string for the thumb instruction "insn1". 265 // If "insn1" is a BL or BLX instruction that is the first of two Thumb 266 // instructions, then insn2 is the second of two instructions. Otherwise, 267 // insn2 is ignored. 268 char *disasm_insn_thumb(uint32_t pc, uint32_t insn1, uint32_t insn2, char *result) 269 { 270 struct thumb_opcode * insn; 271 static char buf[80]; 272 char *ptr; 273 uint32_t addr; 274 int len; 275 276 if (result == NULL) 277 result = buf; 278 ptr = result; 279 280 for (insn = thumb_opcodes; insn->assembler; insn++) { 281 if ((insn1 & insn->mask) != insn->value) 282 continue; 283 284 const char * c = insn->assembler; 285 286 /* Special processing for Thumb 2-instruction BL sequence: */ 287 if (!*c) { /* Check for empty (not NULL) assembler string. */ 288 uint32_t offset; 289 290 offset = BDISP23 (insn1, insn2); 291 offset = offset * 2 + pc + 4; 292 293 if ((insn2 & 0x1000) == 0) { 294 len = sprintf(ptr, "blx\t"); 295 offset &= 0xfffffffc; 296 } else { 297 len = sprintf(ptr, "bl\t"); 298 } 299 ptr += len; 300 301 sprintf(ptr, "0x%x", offset); 302 return result; 303 } 304 305 insn1 &= 0xffff; 306 307 for (; *c; c++) { 308 if (*c != '%') { 309 len = sprintf(ptr, "%c", *c); 310 ptr += len; 311 continue; 312 } 313 314 int domaskpc = 0; 315 int domasklr = 0; 316 317 switch (*++c) { 318 case '%': 319 len = sprintf(ptr, "%%"); 320 ptr += len; 321 break; 322 323 case 'S': { 324 uint32_t reg; 325 326 reg = (insn1 >> 3) & 0x7; 327 if (insn1 & (1 << 6)) 328 reg += 8; 329 330 len = sprintf(ptr, "%s", arm_regnames[reg]); 331 ptr += len; 332 break; 333 } 334 335 case 'D': { 336 uint32_t reg; 337 338 reg = insn1 & 0x7; 339 if (insn1 & (1 << 7)) 340 reg += 8; 341 342 len = sprintf(ptr, "%s", arm_regnames[reg]); 343 ptr += len; 344 break; 345 } 346 347 case 'T': 348 len = sprintf(ptr, "%s", 349 arm_conditional [(insn1 >> 8) & 0xf]); 350 ptr += len; 351 break; 352 353 case 'N': 354 if (insn1 & (1 << 8)) 355 domasklr = 1; 356 /* Fall through. */ 357 case 'O': 358 if (*c == 'O' && (insn1 & (1 << 8))) 359 domaskpc = 1; 360 /* Fall through. */ 361 case 'M': { 362 int started = 0; 363 int reg; 364 365 len = sprintf(ptr, "{"); 366 ptr += len; 367 368 /* It would be nice if we could spot 369 ranges, and generate the rS-rE format: */ 370 for (reg = 0; (reg < 8); reg++) 371 if ((insn1 & (1 << reg)) != 0) { 372 if (started) { 373 len = sprintf(ptr, ", "); 374 ptr += len; 375 } 376 started = 1; 377 len = sprintf(ptr, "%s", arm_regnames[reg]); 378 ptr += len; 379 } 380 381 if (domasklr) { 382 if (started) { 383 len = sprintf(ptr, ", "); 384 ptr += len; 385 } 386 started = 1; 387 len = sprintf(ptr, arm_regnames[14] /* "lr" */); 388 ptr += len; 389 } 390 391 if (domaskpc) { 392 if (started) { 393 len = sprintf(ptr, ", "); 394 ptr += len; 395 } 396 len = sprintf(ptr, arm_regnames[15] /* "pc" */); 397 ptr += len; 398 } 399 400 len = sprintf(ptr, "}"); 401 ptr += len; 402 break; 403 } 404 405 case '0': case '1': case '2': case '3': case '4': 406 case '5': case '6': case '7': case '8': case '9': { 407 int bitstart = *c++ - '0'; 408 int bitend = 0; 409 410 while (*c >= '0' && *c <= '9') 411 bitstart = (bitstart * 10) + *c++ - '0'; 412 413 switch (*c) { 414 case '-': { 415 uint32_t reg; 416 417 c++; 418 while (*c >= '0' && *c <= '9') 419 bitend = (bitend * 10) + *c++ - '0'; 420 if (!bitend) 421 abort (); 422 reg = insn1 >> bitstart; 423 reg &= (2 << (bitend - bitstart)) - 1; 424 switch (*c) { 425 case 'r': 426 len = sprintf(ptr, "%s", arm_regnames[reg]); 427 break; 428 429 case 'd': 430 len = sprintf(ptr, "%d", reg); 431 break; 432 433 case 'H': 434 len = sprintf(ptr, "%d", reg << 1); 435 break; 436 437 case 'W': 438 len = sprintf(ptr, "%d", reg << 2); 439 break; 440 441 case 'a': 442 /* PC-relative address -- the bottom two 443 bits of the address are dropped 444 before the calculation. */ 445 addr = ((pc + 4) & ~3) + (reg << 2); 446 len = sprintf(ptr, "0x%x", addr); 447 break; 448 449 case 'x': 450 len = sprintf(ptr, "0x%04x", reg); 451 break; 452 453 case 'I': 454 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 455 len = sprintf(ptr, "%d", reg); 456 break; 457 458 case 'B': 459 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 460 addr = reg * 2 + pc + 4; 461 len = sprintf(ptr, "0x%x", addr); 462 break; 463 464 default: 465 abort (); 466 } 467 ptr += len; 468 break; 469 } 470 471 case '\'': 472 c++; 473 if ((insn1 & (1 << bitstart)) != 0) { 474 len = sprintf(ptr, "%c", *c); 475 ptr += len; 476 } 477 break; 478 479 case '?': 480 ++c; 481 if ((insn1 & (1 << bitstart)) != 0) 482 len = sprintf(ptr, "%c", *c++); 483 else 484 len = sprintf(ptr, "%c", *++c); 485 ptr += len; 486 break; 487 488 default: 489 abort (); 490 } 491 break; 492 } 493 494 default: 495 abort (); 496 } 497 } 498 return result; 499 } 500 501 /* No match. */ 502 abort (); 503 } 504
