Lines Matching refs:Op
42 static MachineOperand earlyUseOperand(MachineOperand Op) {
43 if (Op.isReg())
44 Op.setIsKill(false);
45 return Op;
240 // structure, but VAEND is a no-op.
479 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
489 Op.getValueType()));
493 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
496 Op.getValueType()));
500 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
503 Op.getValueType()));
507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
510 Op.getValueType()));
514 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
517 Op.getValueType()));
521 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1105 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1106 SDValue Chain = Op.getOperand(0);
1107 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1108 SDValue CmpOp0 = Op.getOperand(2);
1109 SDValue CmpOp1 = Op.getOperand(3);
1110 SDValue Dest = Op.getOperand(4);
1111 SDLoc DL(Op);
1115 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1120 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
1122 SDValue CmpOp0 = Op.getOperand(0);
1123 SDValue CmpOp1 = Op.getOperand(1);
1124 SDValue TrueOp = Op.getOperand(2);
1125 SDValue FalseOp = Op.getOperand(3);
1126 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1127 SDLoc DL(Op);
1139 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1260 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
1262 SDLoc DL(Op);
1263 SDValue In = Op.getOperand(0);
1265 EVT ResVT = Op.getValueType();
1289 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
1296 SDValue Chain = Op.getOperand(0);
1297 SDValue Addr = Op.getOperand(1);
1298 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1299 SDLoc DL(Op);
1326 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
1328 SDValue Chain = Op.getOperand(0);
1329 SDValue DstPtr = Op.getOperand(1);
1330 SDValue SrcPtr = Op.getOperand(2);
1331 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1332 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1333 SDLoc DL(Op);
1341 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
1342 SDValue Chain = Op.getOperand(0);
1343 SDValue Size = Op.getOperand(1);
1344 SDLoc DL(Op);
1367 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
1369 EVT VT = Op.getValueType();
1370 SDLoc DL(Op);
1378 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1382 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
1384 SDValue Op0 = Op.getOperand(0);
1385 SDValue Op1 = Op.getOperand(1);
1386 EVT VT = Op.getValueType();
1387 SDLoc DL(Op);
1409 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
1411 EVT VT = Op.getValueType();
1412 SDLoc DL(Op);
1420 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1423 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1427 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
1428 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
1431 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1446 return Op;
1453 return Op;
1460 return Op;
1477 SDLoc DL(Op);
1485 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
1487 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
1490 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
1496 return Op;
1561 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
1563 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
1569 return Op;
1605 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
1609 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
1610 SystemZ::R15D, Op.getValueType());
1613 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
1617 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
1618 SystemZ::R15D, Op.getOperand(1));
1621 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
1623 switch (Op.getOpcode()) {
1625 return lowerBR_CC(Op, DAG);
1627 return lowerSELECT_CC(Op, DAG);
1629 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
1631 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
1633 Op), DAG);
1635 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
1637 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
1639 return lowerBITCAST(Op, DAG);
1641 return lowerVASTART(Op, DAG);
1643 return lowerVACOPY(Op, DAG);
1645 return lowerDYNAMIC_STACKALLOC(Op, DAG);
1647 return lowerUMUL_LOHI(Op, DAG);
1649 return lowerSDIVREM(Op, DAG);
1651 return lowerUDIVREM(Op, DAG);
1653 return lowerOR(Op, DAG);
1655 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_SWAPW);
1657 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
1659 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
1661 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
1663 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
1665 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
1667 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
1669 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
1671 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
1673 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
1675 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
1677 return lowerATOMIC_CMP_SWAP(Op, DAG);
1679 return lowerSTACKSAVE(Op, DAG);
1681 return lowerSTACKRESTORE(Op, DAG);
1918 // %RotatedNewVal = OP %RotatedOldVal, %Src2
