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      1 
      2 /*---------------------------------------------------------------*/
      3 /*--- begin                                  host_mips_defs.h ---*/
      4 /*---------------------------------------------------------------*/
      5 
      6 /*
      7    This file is part of Valgrind, a dynamic binary instrumentation
      8    framework.
      9 
     10    Copyright (C) 2010-2012 RT-RK
     11       mips-valgrind (at) rt-rk.com
     12 
     13    This program is free software; you can redistribute it and/or
     14    modify it under the terms of the GNU General Public License as
     15    published by the Free Software Foundation; either version 2 of the
     16    License, or (at your option) any later version.
     17 
     18    This program is distributed in the hope that it will be useful, but
     19    WITHOUT ANY WARRANTY; without even the implied warranty of
     20    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     21    General Public License for more details.
     22 
     23    You should have received a copy of the GNU General Public License
     24    along with this program; if not, write to the Free Software
     25    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
     26    02111-1307, USA.
     27 
     28    The GNU General Public License is contained in the file COPYING.
     29 */
     30 
     31 #ifndef __VEX_HOST_MIPS_DEFS_H
     32 #define __VEX_HOST_MIPS_DEFS_H
     33 
     34 /* Num registers used for function calls */
     35 #define MIPS_N_REGPARMS 4
     36 
     37 /* --------- Registers. --------- */
     38 
     39 /* The usual HReg abstraction.
     40    There are 32 general purpose regs.
     41 */
     42 
     43 extern void ppHRegMIPS(HReg, Bool);
     44 
     45 extern HReg hregMIPS_GPR0(Bool mode64);   // scratch reg / zero reg
     46 extern HReg hregMIPS_GPR1(Bool mode64);   // reserved for trap handling
     47 extern HReg hregMIPS_GPR2(Bool mode64);   // reserved for trap handling
     48 extern HReg hregMIPS_GPR3(Bool mode64);
     49 extern HReg hregMIPS_GPR4(Bool mode64);
     50 extern HReg hregMIPS_GPR5(Bool mode64);
     51 extern HReg hregMIPS_GPR6(Bool mode64);
     52 extern HReg hregMIPS_GPR7(Bool mode64);
     53 extern HReg hregMIPS_GPR8(Bool mode64);
     54 extern HReg hregMIPS_GPR9(Bool mode64);
     55 extern HReg hregMIPS_GPR10(Bool mode64);
     56 extern HReg hregMIPS_GPR11(Bool mode64);
     57 extern HReg hregMIPS_GPR12(Bool mode64);
     58 extern HReg hregMIPS_GPR13(Bool mode64);
     59 extern HReg hregMIPS_GPR14(Bool mode64);
     60 extern HReg hregMIPS_GPR15(Bool mode64);
     61 extern HReg hregMIPS_GPR16(Bool mode64);
     62 extern HReg hregMIPS_GPR17(Bool mode64);
     63 extern HReg hregMIPS_GPR18(Bool mode64);
     64 extern HReg hregMIPS_GPR19(Bool mode64);
     65 extern HReg hregMIPS_GPR20(Bool mode64);
     66 extern HReg hregMIPS_GPR21(Bool mode64);
     67 extern HReg hregMIPS_GPR22(Bool mode64);
     68 extern HReg hregMIPS_GPR23(Bool mode64);  // GuestStatePtr
     69 extern HReg hregMIPS_GPR24(Bool mode64);  // reserved for dispatcher
     70 extern HReg hregMIPS_GPR25(Bool mode64);
     71 extern HReg hregMIPS_GPR26(Bool mode64);
     72 extern HReg hregMIPS_GPR27(Bool mode64);
     73 extern HReg hregMIPS_GPR28(Bool mode64);
     74 extern HReg hregMIPS_GPR29(Bool mode64);
     75 extern HReg hregMIPS_GPR30(Bool mode64);
     76 extern HReg hregMIPS_GPR31(Bool mode64);
     77 extern HReg hregMIPS_PC(Bool mode64);
     78 
     79 extern HReg hregMIPS_HI(Bool mode64);
     80 extern HReg hregMIPS_LO(Bool mode64);
     81 
     82 extern HReg hregMIPS_F0(Bool mode64);
     83 extern HReg hregMIPS_F1(Bool mode64);
     84 extern HReg hregMIPS_F2(Bool mode64);
     85 extern HReg hregMIPS_F3(Bool mode64);
     86 extern HReg hregMIPS_F4(Bool mode64);
     87 extern HReg hregMIPS_F5(Bool mode64);
     88 extern HReg hregMIPS_F6(Bool mode64);
     89 extern HReg hregMIPS_F7(Bool mode64);
     90 extern HReg hregMIPS_F8(Bool mode64);
     91 extern HReg hregMIPS_F9(Bool mode64);
     92 extern HReg hregMIPS_F10(Bool mode64);
     93 extern HReg hregMIPS_F11(Bool mode64);
     94 extern HReg hregMIPS_F12(Bool mode64);
     95 extern HReg hregMIPS_F13(Bool mode64);
     96 extern HReg hregMIPS_F14(Bool mode64);
     97 extern HReg hregMIPS_F15(Bool mode64);
     98 extern HReg hregMIPS_F16(Bool mode64);
     99 extern HReg hregMIPS_F17(Bool mode64);
    100 extern HReg hregMIPS_F18(Bool mode64);
    101 extern HReg hregMIPS_F19(Bool mode64);
    102 extern HReg hregMIPS_F20(Bool mode64);
    103 extern HReg hregMIPS_F21(Bool mode64);
    104 extern HReg hregMIPS_F22(Bool mode64);
    105 extern HReg hregMIPS_F23(Bool mode64);
    106 extern HReg hregMIPS_F24(Bool mode64);
    107 extern HReg hregMIPS_F25(Bool mode64);
    108 extern HReg hregMIPS_F26(Bool mode64);
    109 extern HReg hregMIPS_F27(Bool mode64);
    110 extern HReg hregMIPS_F28(Bool mode64);
    111 extern HReg hregMIPS_F29(Bool mode64);
    112 extern HReg hregMIPS_F30(Bool mode64);
    113 extern HReg hregMIPS_F31(Bool mode64);
    114 extern HReg hregMIPS_FIR(void);
    115 extern HReg hregMIPS_FCCR(void);
    116 extern HReg hregMIPS_FEXR(void);
    117 extern HReg hregMIPS_FENR(void);
    118 extern HReg hregMIPS_FCSR(void);
    119 extern HReg hregMIPS_COND(void);
    120 
    121 extern HReg hregMIPS_D0(void);
    122 extern HReg hregMIPS_D1(void);
    123 extern HReg hregMIPS_D2(void);
    124 extern HReg hregMIPS_D3(void);
    125 extern HReg hregMIPS_D4(void);
    126 extern HReg hregMIPS_D5(void);
    127 extern HReg hregMIPS_D6(void);
    128 extern HReg hregMIPS_D7(void);
    129 extern HReg hregMIPS_D8(void);
    130 extern HReg hregMIPS_D9(void);
    131 extern HReg hregMIPS_D10(void);
    132 extern HReg hregMIPS_D11(void);
    133 extern HReg hregMIPS_D12(void);
    134 extern HReg hregMIPS_D13(void);
    135 extern HReg hregMIPS_D14(void);
    136 extern HReg hregMIPS_D15(void);
    137 
    138 #define GuestStatePointer(_mode64)     hregMIPS_GPR10(_mode64)
    139 
    140 #define StackFramePointer(_mode64)     hregMIPS_GPR30(_mode64)
    141 #define LinkRegister(_mode64)          hregMIPS_GPR31(_mode64)
    142 #define StackPointer(_mode64)          hregMIPS_GPR29(_mode64)
    143 #define FCSR()                         hregMIPS_FCSR()
    144 #define COND()                         hregMIPS_COND()
    145 
    146 #define HIRegister(_mode64)        hregMIPS_HI(_mode64)
    147 #define LORegister(_mode64)        hregMIPS_LO(_mode64)
    148 
    149 /* a0, a1, a2, a3 */
    150 #define MIPS_N_ARGREGS 4
    151 
    152 /* --------- Condition codes, Intel encoding. --------- */
    153 typedef enum {
    154    MIPScc_EQ = 0,    /* equal */
    155    MIPScc_NE = 1,    /* not equal */
    156 
    157    MIPScc_HS = 2,    /* >=u (higher or same) */
    158    MIPScc_LO = 3,    /* <u  (lower) */
    159 
    160    MIPScc_MI = 4,    /* minus (negative) */
    161    MIPScc_PL = 5,    /* plus (zero or +ve) */
    162 
    163    MIPScc_VS = 6,    /* overflow */
    164    MIPScc_VC = 7,    /* no overflow */
    165 
    166    MIPScc_HI = 8,    /* >u   (higher) */
    167    MIPScc_LS = 9,    /* <=u  (lower or same) */
    168 
    169    MIPScc_GE = 10,      /* >=s (signed greater or equal) */
    170    MIPScc_LT = 11,      /* <s  (signed less than) */
    171 
    172    MIPScc_GT = 12,      /* >s  (signed greater) */
    173    MIPScc_LE = 13,      /* <=s (signed less or equal) */
    174 
    175    MIPScc_AL = 14,      /* always (unconditional) */
    176    MIPScc_NV = 15    /* never (unconditional): */
    177 } MIPSCondCode;
    178 
    179 extern HChar *showMIPSCondCode(MIPSCondCode);
    180 
    181 /* --------- Memory address expressions (amodes). --------- */
    182 typedef enum {
    183    Mam_IR,        /* Immediate (signed 16-bit) + Reg */
    184    Mam_RR         /* Reg1 + Reg2 */
    185 } MIPSAModeTag;
    186 
    187 typedef struct {
    188    MIPSAModeTag tag;
    189    union {
    190       struct {
    191          HReg base;
    192          Int index;
    193       } IR;
    194       struct {
    195          HReg base;
    196          HReg index;
    197       } RR;
    198    } Mam;
    199 } MIPSAMode;
    200 
    201 extern MIPSAMode *MIPSAMode_IR(Int, HReg);
    202 extern MIPSAMode *MIPSAMode_RR(HReg, HReg);
    203 
    204 extern MIPSAMode *dopyMIPSAMode(MIPSAMode *);
    205 extern MIPSAMode *nextMIPSAModeFloat(MIPSAMode *);
    206 extern MIPSAMode *nextMIPSAModeInt(MIPSAMode *);
    207 
    208 extern void ppMIPSAMode(MIPSAMode *, Bool);
    209 
    210 /* --------- Operand, which can be a reg or a u16/s16. --------- */
    211 /* ("RH" == "Register or Halfword immediate") */
    212 typedef enum {
    213    Mrh_Imm,
    214    Mrh_Reg
    215 } MIPSRHTag;
    216 
    217 typedef struct {
    218    MIPSRHTag tag;
    219    union {
    220       struct {
    221          Bool syned;
    222          UShort imm16;
    223       } Imm;
    224       struct {
    225          HReg reg;
    226       } Reg;
    227    } Mrh;
    228 } MIPSRH;
    229 
    230 extern void ppMIPSRH(MIPSRH *, Bool);
    231 
    232 extern MIPSRH *MIPSRH_Imm(Bool, UShort);
    233 extern MIPSRH *MIPSRH_Reg(HReg);
    234 
    235 /* --- Addressing Mode suitable for VFP --- */
    236 typedef struct {
    237    HReg reg;
    238    Int simm11;
    239 } MIPSAModeV;
    240 
    241 extern MIPSAModeV *mkMIPSAModeV(HReg reg, Int simm11);
    242 
    243 extern void ppMIPSAModeV(MIPSAModeV *);
    244 
    245 /* --------- Reg or imm-8x4 operands --------- */
    246 /* a.k.a (a very restricted form of) Shifter Operand,
    247    in the MIPS parlance. */
    248 
    249 typedef enum {
    250    MIPSri84_I84 = 5, /* imm8 `ror` (2 * imm4) */
    251    MIPSri84_R     /* reg */
    252 } MIPSRI84Tag;
    253 
    254 typedef struct {
    255    MIPSRI84Tag tag;
    256    union {
    257       struct {
    258          UShort imm8;
    259          UShort imm4;
    260       } I84;
    261       struct {
    262          HReg reg;
    263       } R;
    264    } MIPSri84;
    265 } MIPSRI84;
    266 
    267 extern MIPSRI84 *MIPSRI84_I84(UShort imm8, UShort imm4);
    268 extern MIPSRI84 *MIPSRI84_R(HReg);
    269 
    270 extern void ppMIPSRI84(MIPSRI84 *);
    271 
    272 /* --------- Reg or imm5 operands --------- */
    273 typedef enum {
    274    MIPSri5_I5 = 7,      /* imm5, 1 .. 31 only (no zero!) */
    275    MIPSri5_R      /* reg */
    276 } MIPSRI5Tag;
    277 
    278 typedef struct {
    279    MIPSRI5Tag tag;
    280    union {
    281       struct {
    282          UInt imm5;
    283       } I5;
    284       struct {
    285          HReg reg;
    286       } R;
    287    } MIPSri5;
    288 } MIPSRI5;
    289 
    290 extern MIPSRI5 *MIPSRI5_I5(UInt imm5);
    291 extern MIPSRI5 *MIPSRI5_R(HReg);
    292 
    293 extern void ppMIPSRI5(MIPSRI5 *);
    294 
    295 /* --------- Instructions. --------- */
    296 
    297 /*Tags for operations*/
    298 
    299 /* --------- */
    300 typedef enum {
    301    Mun_CLO,
    302    Mun_CLZ,
    303    Mun_NOP,
    304 } MIPSUnaryOp;
    305 
    306 extern HChar *showMIPSUnaryOp(MIPSUnaryOp);
    307 /* --------- */
    308 
    309 /* --------- */
    310 
    311 typedef enum {
    312    Malu_INVALID,
    313    Malu_ADD, Malu_SUB,
    314    Malu_AND, Malu_OR, Malu_NOR, Malu_XOR,
    315 } MIPSAluOp;
    316 
    317 extern HChar *showMIPSAluOp(MIPSAluOp,
    318                             Bool /* is the 2nd operand an immediate? */ );
    319 
    320 /* --------- */
    321 typedef enum {
    322    Mshft_INVALID,
    323    Mshft_SLL, Mshft_SRL,
    324    Mshft_SRA
    325 } MIPSShftOp;
    326 
    327 extern HChar *showMIPSShftOp(MIPSShftOp,
    328                              Bool /* is the 2nd operand an immediate? */ ,
    329                              Bool /* is this a 32bit or 64bit op? */ );
    330 
    331 /* --------- */
    332 typedef enum {
    333    Macc_ADD,
    334    Macc_SUB
    335 } MIPSMaccOp;
    336 
    337 extern HChar *showMIPSMaccOp(MIPSMaccOp, Bool);
    338 /* --------- */
    339 
    340 /* ----- Instruction tags ----- */
    341 typedef enum {
    342    Min_LI,        /* load word (32/64-bit) immediate (fake insn) */
    343    Min_Alu,    /* word add/sub/and/or/xor/nor/others? */
    344    Min_Shft,      /* word sll/srl/sra */
    345    Min_Unary,     /* clo, clz, nop, neg */
    346 
    347    Min_Cmp,    /* word compare (fake insn) */
    348 
    349    Min_Mul,    /* widening/non-widening multiply */
    350    Min_Div,    /* div */
    351 
    352    Min_Call,      /* call to address in register */
    353 
    354    /* The following 5 insns are mandated by translation chaining */
    355    Min_XDirect,     /* direct transfer to GA */
    356    Min_XIndir,      /* indirect transfer to GA */
    357    Min_XAssisted,   /* assisted transfer to GA */
    358    Min_EvCheck,     /* Event check */
    359    Min_ProfInc,     /* 64-bit profile counter increment */
    360 
    361    Min_RdWrLR,    /* Read/Write Link Register */
    362    Min_Mthi,      /* Move to HI from GP register */
    363    Min_Mtlo,      /* Move to LO from GP register */
    364    Min_Mfhi,      /* Move from HI to GP register */
    365    Min_Mflo,      /* Move from LO to GP register */
    366    Min_Macc,      /* Multiply and accumulate */
    367 
    368    Min_Load,      /* zero-extending load a 8|16|32 bit value from mem */
    369    Min_Store,     /* store a 8|16|32 bit value to mem */
    370    Min_LoadL,     /* mips Load Linked Word */
    371    Min_StoreC,    /* mips Store Conditional Word */
    372 
    373    Min_FpUnary,      /* FP unary op */
    374    Min_FpBinary,     /* FP binary op */
    375    Min_FpConvert,    /* FP conversion op */
    376    Min_FpMulAcc,     /* FP multipy-accumulate style op */
    377    Min_FpLdSt,    /* FP load/store */
    378    Min_FpSTFIW,      /* stfiwx */
    379    Min_FpRSP,     /* FP round IEEE754 double to IEEE754 single */
    380    Min_FpCftI,    /* fcfid/fctid/fctiw */
    381    Min_FpCMov,    /* FP floating point conditional move */
    382    Min_MtFCSR,    /* set FCSR register */
    383    Min_MfFCSR,    /* get FCSR register */
    384    Min_FpCompare,    /* FP compare, generating value into int reg */
    385    Min_MovCond
    386 } MIPSInstrTag;
    387 
    388 /* --------- */
    389 typedef enum {
    390    Mfp_INVALID,
    391 
    392    /* Ternary */
    393    Mfp_MADDD, Mfp_MSUBD,
    394    Mfp_MADDS, Mfp_MSUBS,
    395 
    396    /* Binary */
    397    Mfp_ADDD, Mfp_SUBD, Mfp_MULD, Mfp_DIVD,
    398    Mfp_ADDS, Mfp_SUBS, Mfp_MULS, Mfp_DIVS, Mfp_CVTSD, Mfp_CVTSW, Mfp_CVTWD,
    399    Mfp_CVTWS, Mfp_TRULS, Mfp_TRULD, Mfp_TRUWS, Mfp_TRUWD, Mfp_FLOORWS,
    400    Mfp_FLOORWD, Mfp_ROUNDWS, Mfp_ROUNDWD, Mfp_CVTDW, Mfp_CMP,
    401    Mfp_CEILWS, Mfp_CEILWD, Mfp_CEILLS, Mfp_CEILLD,
    402 
    403    /* Unary */
    404    Mfp_SQRTS, Mfp_SQRTD, Mfp_RSQRTS, Mfp_RSQRTD, Mfp_RECIPS, Mfp_RECIPD,
    405    Mfp_ABSS, Mfp_ABSD, Mfp_NEGS, Mfp_NEGD, Mfp_MOVS, Mfp_MOVD,
    406    Mfp_RES, Mfp_RSQRTE, Mfp_FRIN, Mfp_FRIM, Mfp_FRIP, Mfp_FRIZ, Mfp_CVTD
    407 } MIPSFpOp;
    408 
    409 extern HChar *showMIPSFpOp(MIPSFpOp);
    410 
    411 /*--------- Structure for instructions ----------*/
    412 /* Destinations are on the LEFT (first operand) */
    413 
    414 typedef struct {
    415    MIPSInstrTag tag;
    416    union {
    417       /* Get a 32/64-bit literal into a register.
    418          May turn into a number of real insns. */
    419       struct {
    420          HReg dst;
    421          ULong imm;
    422       } LI;
    423       /* Integer add/sub/and/or/xor.  Limitations:
    424          - For add, the immediate, if it exists, is a signed 16.
    425          - For sub, the immediate, if it exists, is a signed 16
    426          which may not be -32768, since no such instruction
    427          exists, and so we have to emit addi with +32768, but
    428          that is not possible.
    429          - For and/or/xor,  the immediate, if it exists,
    430          is an unsigned 16.
    431        */
    432       struct {
    433          MIPSAluOp op;
    434          HReg dst;
    435          HReg srcL;
    436          MIPSRH *srcR;
    437       } Alu;
    438       /* Integer shl/shr/sar.
    439          Limitations: the immediate, if it exists,
    440          is a signed 5-bit value between 1 and 31 inclusive.
    441        */
    442       struct {
    443          MIPSShftOp op;
    444          Bool sz32;  /* mode64 has both 32 and 64bit shft */
    445          HReg dst;
    446          HReg srcL;
    447          MIPSRH *srcR;
    448       } Shft;
    449       /* Clz, Clo, nop */
    450       struct {
    451          MIPSUnaryOp op;
    452          HReg dst;
    453          HReg src;
    454       } Unary;
    455       /* Word compare. Fake instruction, used for basic block ending */
    456       struct {
    457          Bool syned;
    458          Bool sz32;
    459          HReg dst;
    460          HReg srcL;
    461          HReg srcR;
    462 
    463          MIPSCondCode cond;
    464       } Cmp;
    465       struct {
    466          Bool widening; //True => widening, False => non-widening
    467          Bool syned; //signed/unsigned - meaningless if widenind = False
    468          Bool sz32;
    469          HReg dst;
    470          HReg srcL;
    471          HReg srcR;
    472       } Mul;
    473       struct {
    474          Bool syned; //signed/unsigned - meaningless if widenind = False
    475          Bool sz32;
    476          HReg srcL;
    477          HReg srcR;
    478       } Div;
    479       /* Pseudo-insn.  Call target (an absolute address), on given
    480          condition (which could be Mcc_ALWAYS).  argiregs indicates
    481          which of r3 .. r10
    482          carries argument values for this call,
    483          using a bit mask (1<<N is set if rN holds an arg, for N in
    484          3 .. 10 inclusive).
    485          If cond is != Mcc_ALWAYS, src is checked.
    486          Otherwise, unconditional call */
    487       struct {
    488          MIPSCondCode cond;
    489          Addr32 target;
    490          UInt argiregs;
    491          HReg src;
    492       } Call;
    493       /* Update the guest EIP value, then exit requesting to chain
    494          to it.  May be conditional.  Urr, use of Addr32 implicitly
    495          assumes that wordsize(guest) == wordsize(host). */
    496       struct {
    497          Addr32      dstGA;    /* next guest address */
    498          MIPSAMode*   amPC;    /* amode in guest state for PC */
    499          MIPSCondCode cond;     /* can be MIPScc_AL */
    500          Bool        toFastEP; /* chain to the slow or fast point? */
    501       } XDirect;
    502       /* Boring transfer to a guest address not known at JIT time.
    503          Not chainable.  May be conditional. */
    504       struct {
    505          HReg        dstGA;
    506          MIPSAMode*   amPC;
    507          MIPSCondCode cond; /* can be MIPScc_AL */
    508       } XIndir;
    509       /* Assisted transfer to a guest address, most general case.
    510          Not chainable.  May be conditional. */
    511       struct {
    512          HReg        dstGA;
    513          MIPSAMode*   amPC;
    514          MIPSCondCode cond; /* can be MIPScc_AL */
    515          IRJumpKind  jk;
    516       } XAssisted;
    517       /* Zero extending loads.  Dst size is host word size */
    518       struct {
    519          UChar sz;   /* 1|2|4|8 */
    520          HReg dst;
    521          MIPSAMode *src;
    522       } Load;
    523       /* 64/32/16/8 bit stores */
    524       struct {
    525          UChar sz;   /* 1|2|4|8 */
    526          MIPSAMode *dst;
    527          HReg src;
    528       } Store;
    529       struct {
    530          UChar sz;   /* 4|8 */
    531          HReg dst;
    532          MIPSAMode *src;
    533       } LoadL;
    534       struct {
    535          UChar sz;   /* 4|8 */
    536          MIPSAMode *dst;
    537          HReg src;
    538       } StoreC;
    539       /* Move from HI/LO register to GP register. */
    540       struct {
    541          HReg dst;
    542       } MfHL;
    543 
    544       /* Move to HI/LO register from GP register. */
    545       struct {
    546          HReg src;
    547       } MtHL;
    548 
    549       /* Read/Write Link Register */
    550       struct {
    551          Bool wrLR;
    552          HReg gpr;
    553       } RdWrLR;
    554 
    555       /* MIPS Multiply and accumulate instructions. */
    556       struct {
    557          MIPSMaccOp op;
    558          Bool syned;
    559 
    560          HReg srcL;
    561          HReg srcR;
    562       } Macc;
    563 
    564       /* MIPS Floating point */
    565       struct {
    566          MIPSFpOp op;
    567          HReg dst;
    568          HReg src;
    569       } FpUnary;
    570       struct {
    571          MIPSFpOp op;
    572          HReg dst;
    573          HReg srcL;
    574          HReg srcR;
    575       } FpBinary;
    576       struct {
    577          MIPSFpOp op;
    578          HReg dst;
    579          HReg srcML;
    580          HReg srcMR;
    581          HReg srcAcc;
    582       } FpMulAcc;
    583       struct {
    584          Bool isLoad;
    585          UChar sz;   /* only 4 (IEEE single) or 8 (IEEE double) */
    586          HReg reg;
    587          MIPSAMode *addr;
    588       } FpLdSt;
    589 
    590       struct {
    591          MIPSFpOp op;
    592          HReg dst;
    593          HReg src;
    594       } FpConvert;
    595       struct {
    596          MIPSFpOp op;
    597          HReg dst;
    598          HReg srcL;
    599          HReg srcR;
    600          UChar cond1;
    601       } FpCompare;
    602       struct {
    603          MIPSFpOp op;
    604          HReg dst;
    605          HReg srcL;
    606          MIPSRH *srcR;
    607          HReg condR;
    608          MIPSCondCode cond;
    609       } MovCond;
    610       /* Move from GP register to FCSR register. */
    611       struct {
    612          HReg src;
    613       } MtFCSR;
    614       /* Move from FCSR register to GP register. */
    615       struct {
    616          HReg dst;
    617       } MfFCSR;
    618       struct {
    619          MIPSAMode* amCounter;
    620          MIPSAMode* amFailAddr;
    621       } EvCheck;
    622       struct {
    623          /* No fields.  The address of the counter to inc is
    624             installed later, post-translation, by patching it in,
    625             as it is not known at translation time. */
    626       } ProfInc;
    627 
    628    } Min;
    629 } MIPSInstr;
    630 
    631 extern MIPSInstr *MIPSInstr_LI(HReg, ULong);
    632 extern MIPSInstr *MIPSInstr_Alu(MIPSAluOp, HReg, HReg, MIPSRH *);
    633 extern MIPSInstr *MIPSInstr_Shft(MIPSShftOp, Bool sz32, HReg, HReg, MIPSRH *);
    634 extern MIPSInstr *MIPSInstr_Unary(MIPSUnaryOp op, HReg dst, HReg src);
    635 extern MIPSInstr *MIPSInstr_Cmp(Bool, Bool, HReg, HReg, HReg, MIPSCondCode);
    636 
    637 extern MIPSInstr *MIPSInstr_Mul(Bool syned, Bool hi32, Bool sz32, HReg,
    638                                 HReg, HReg);
    639 extern MIPSInstr *MIPSInstr_Div(Bool syned, Bool sz32, HReg, HReg);
    640 extern MIPSInstr *MIPSInstr_Madd(Bool, HReg, HReg);
    641 extern MIPSInstr *MIPSInstr_Msub(Bool, HReg, HReg);
    642 
    643 extern MIPSInstr *MIPSInstr_Load(UChar sz, HReg dst, MIPSAMode * src,
    644                                  Bool mode64);
    645 extern MIPSInstr *MIPSInstr_Store(UChar sz, MIPSAMode * dst, HReg src,
    646                                   Bool mode64);
    647 
    648 extern MIPSInstr *MIPSInstr_LoadL(UChar sz, HReg dst, MIPSAMode * src,
    649                                   Bool mode64);
    650 extern MIPSInstr *MIPSInstr_StoreC(UChar sz, MIPSAMode * dst, HReg src,
    651                                    Bool mode64);
    652 
    653 extern MIPSInstr *MIPSInstr_Call(MIPSCondCode, Addr32, UInt, HReg);
    654 extern MIPSInstr *MIPSInstr_CallAlways(MIPSCondCode, Addr32, UInt);
    655 
    656 extern MIPSInstr *MIPSInstr_XDirect(Addr32 dstGA, MIPSAMode* amPC,
    657                                      MIPSCondCode cond, Bool toFastEP);
    658 extern MIPSInstr *MIPSInstr_XIndir(HReg dstGA, MIPSAMode* amPC,
    659                                      MIPSCondCode cond);
    660 extern MIPSInstr *MIPSInstr_XAssisted(HReg dstGA, MIPSAMode* amPC,
    661                                       MIPSCondCode cond, IRJumpKind jk);
    662 
    663 extern MIPSInstr *MIPSInstr_FpUnary(MIPSFpOp op, HReg dst, HReg src);
    664 extern MIPSInstr *MIPSInstr_FpBinary(MIPSFpOp op, HReg dst, HReg srcL,
    665                                      HReg srcR);
    666 extern MIPSInstr *MIPSInstr_FpConvert(MIPSFpOp op, HReg dst, HReg src);
    667 extern MIPSInstr *MIPSInstr_FpCompare(MIPSFpOp op, HReg dst, HReg srcL,
    668                   HReg srcR, UChar cond1);
    669 extern MIPSInstr *MIPSInstr_FpMulAcc(MIPSFpOp op, HReg dst, HReg srcML,
    670                                      HReg srcMR, HReg srcAcc);
    671 extern MIPSInstr *MIPSInstr_FpLdSt(Bool isLoad, UChar sz, HReg, MIPSAMode *);
    672 extern MIPSInstr *MIPSInstr_FpSTFIW(HReg addr, HReg data);
    673 extern MIPSInstr *MIPSInstr_FpRSP(HReg dst, HReg src);
    674 extern MIPSInstr *MIPSInstr_FpCftI(Bool fromI, Bool int32, HReg dst, HReg src);
    675 extern MIPSInstr *MIPSInstr_FpCMov(MIPSCondCode, HReg dst, HReg src);
    676 extern MIPSInstr *MIPSInstr_MtFCSR(HReg src);
    677 extern MIPSInstr *MIPSInstr_MfFCSR(HReg dst);
    678 extern MIPSInstr *MIPSInstr_FpCmp(HReg dst, HReg srcL, HReg srcR);
    679 
    680 extern MIPSInstr *MIPSInstr_Mfhi(HReg dst);
    681 extern MIPSInstr *MIPSInstr_Mflo(HReg dst);
    682 extern MIPSInstr *MIPSInstr_Mthi(HReg src);
    683 extern MIPSInstr *MIPSInstr_Mtlo(HReg src);
    684 
    685 extern MIPSInstr *MIPSInstr_RdWrLR(Bool wrLR, HReg gpr);
    686 
    687 // srcL will be copied if !condR
    688 extern MIPSInstr *MIPSInstr_MovCond(HReg dst, HReg srcL, MIPSRH * src,
    689                                     HReg condR, MIPSCondCode cond);
    690 
    691 extern MIPSInstr *MIPSInstr_EvCheck(MIPSAMode* amCounter,
    692                                     MIPSAMode* amFailAddr );
    693 extern MIPSInstr *MIPSInstr_ProfInc( void );
    694 
    695 extern void ppMIPSInstr(MIPSInstr *, Bool mode64);
    696 
    697 /* Some functions that insulate the register allocator from details
    698    of the underlying instruction set. */
    699 extern void       getRegUsage_MIPSInstr (HRegUsage *, MIPSInstr *, Bool);
    700 extern void       mapRegs_MIPSInstr     (HRegRemap *, MIPSInstr *, Bool mode64);
    701 extern Bool       isMove_MIPSInstr      (MIPSInstr *, HReg *, HReg *);
    702 extern Int        emit_MIPSInstr        (/*MB_MOD*/Bool* is_profInc,
    703                                          UChar* buf, Int nbuf, MIPSInstr* i,
    704                                          Bool mode64,
    705                                          void* disp_cp_chain_me_to_slowEP,
    706                                          void* disp_cp_chain_me_to_fastEP,
    707                                          void* disp_cp_xindir,
    708                                          void* disp_cp_xassisted );
    709 
    710 extern void genSpill_MIPS ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2,
    711                             HReg rreg, Int offset, Bool);
    712 extern void genReload_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2,
    713                             HReg rreg, Int offset, Bool);
    714 
    715 extern void        getAllocableRegs_MIPS (Int *, HReg **, Bool mode64);
    716 extern HInstrArray *iselSB_MIPS          ( IRSB*,
    717                                            VexArch,
    718                                            VexArchInfo*,
    719                                            VexAbiInfo*,
    720                                            Int offs_Host_EvC_Counter,
    721                                            Int offs_Host_EvC_FailAddr,
    722                                            Bool chainingAllowed,
    723                                            Bool addProfInc,
    724                                            Addr64 max_ga );
    725 
    726 /* How big is an event check?  This is kind of a kludge because it
    727    depends on the offsets of host_EvC_FAILADDR and host_EvC_COUNTER,
    728    and so assumes that they are both <= 128, and so can use the short
    729    offset encoding.  This is all checked with assertions, so in the
    730    worst case we will merely assert at startup. */
    731 extern Int evCheckSzB_MIPS ( void );
    732 
    733 /* Perform a chaining and unchaining of an XDirect jump. */
    734 extern VexInvalRange chainXDirect_MIPS ( void* place_to_chain,
    735                                          void* disp_cp_chain_me_EXPECTED,
    736                                          void* place_to_jump_to,
    737                                          Bool  mode64 );
    738 
    739 extern VexInvalRange unchainXDirect_MIPS ( void* place_to_unchain,
    740                                            void* place_to_jump_to_EXPECTED,
    741                                            void* disp_cp_chain_me,
    742                                            Bool  mode64 );
    743 
    744 /* Patch the counter location into an existing ProfInc point. */
    745 extern VexInvalRange patchProfInc_MIPS ( void*  place_to_patch,
    746                                          ULong* location_of_counter,
    747                                          Bool  mode64 );
    748 
    749 #endif            /* ndef __LIBVEX_HOST_MIPS_HDEFS_H */
    750 
    751 /*---------------------------------------------------------------*/
    752 /*--- end                                    host-mips_defs.h ---*/
    753 /*---------------------------------------------------------------*/
    754