1 //===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef X86REGISTERINFO_H 15 #define X86REGISTERINFO_H 16 17 #include "llvm/Target/TargetRegisterInfo.h" 18 19 #define GET_REGINFO_HEADER 20 #include "X86GenRegisterInfo.inc" 21 22 namespace llvm { 23 class Type; 24 class TargetInstrInfo; 25 class X86TargetMachine; 26 27 class X86RegisterInfo : public X86GenRegisterInfo { 28 public: 29 X86TargetMachine &TM; 30 31 private: 32 /// Is64Bit - Is the target 64-bits. 33 /// 34 bool Is64Bit; 35 36 /// IsWin64 - Is the target on of win64 flavours 37 /// 38 bool IsWin64; 39 40 /// SlotSize - Stack slot size in bytes. 41 /// 42 unsigned SlotSize; 43 44 /// StackPtr - X86 physical register used as stack ptr. 45 /// 46 unsigned StackPtr; 47 48 /// FramePtr - X86 physical register used as frame ptr. 49 /// 50 unsigned FramePtr; 51 52 /// BasePtr - X86 physical register used as a base ptr in complex stack 53 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to 54 /// variable size stack objects. 55 unsigned BasePtr; 56 57 public: 58 X86RegisterInfo(X86TargetMachine &tm); 59 60 // FIXME: This should be tablegen'd like getDwarfRegNum is 61 int getSEHRegNum(unsigned i) const; 62 63 /// getCompactUnwindRegNum - This function maps the register to the number for 64 /// compact unwind encoding. Return -1 if the register isn't valid. 65 int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const; 66 67 /// Code Generation virtual methods... 68 /// 69 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const; 70 71 /// getMatchingSuperRegClass - Return a subclass of the specified register 72 /// class A so that each register in it has a sub-register of the 73 /// specified sub-register index which is in the specified register class B. 74 virtual const TargetRegisterClass * 75 getMatchingSuperRegClass(const TargetRegisterClass *A, 76 const TargetRegisterClass *B, unsigned Idx) const; 77 78 virtual const TargetRegisterClass * 79 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const; 80 81 const TargetRegisterClass* 82 getLargestLegalSuperClass(const TargetRegisterClass *RC) const; 83 84 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 85 /// values. 86 const TargetRegisterClass * 87 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const; 88 89 /// getCrossCopyRegClass - Returns a legal register class to copy a register 90 /// in the specified class to or from. Returns NULL if it is possible to copy 91 /// between a two registers of the specified class. 92 const TargetRegisterClass * 93 getCrossCopyRegClass(const TargetRegisterClass *RC) const; 94 95 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 96 MachineFunction &MF) const; 97 98 /// getCalleeSavedRegs - Return a null-terminated list of all of the 99 /// callee-save registers on this target. 100 const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const; 101 const uint32_t *getCallPreservedMask(CallingConv::ID) const; 102 const uint32_t *getNoPreservedMask() const; 103 104 /// getReservedRegs - Returns a bitset indexed by physical register number 105 /// indicating if a register is a special register that has particular uses and 106 /// should be considered unavailable at all times, e.g. SP, RA. This is used by 107 /// register scavenger to determine what registers are free. 108 BitVector getReservedRegs(const MachineFunction &MF) const; 109 110 bool hasBasePointer(const MachineFunction &MF) const; 111 112 bool canRealignStack(const MachineFunction &MF) const; 113 114 bool needsStackRealignment(const MachineFunction &MF) const; 115 116 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 117 int &FrameIdx) const; 118 119 void eliminateFrameIndex(MachineBasicBlock::iterator MI, 120 int SPAdj, unsigned FIOperandNum, 121 RegScavenger *RS = NULL) const; 122 123 // Debug information queries. 124 unsigned getFrameRegister(const MachineFunction &MF) const; 125 unsigned getStackRegister() const { return StackPtr; } 126 unsigned getBaseRegister() const { return BasePtr; } 127 // FIXME: Move to FrameInfok 128 unsigned getSlotSize() const { return SlotSize; } 129 130 // Exception handling queries. 131 unsigned getEHExceptionRegister() const; 132 unsigned getEHHandlerRegister() const; 133 }; 134 135 // getX86SubSuperRegister - X86 utility function. It returns the sub or super 136 // register of a specific X86 register. 137 // e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX 138 unsigned getX86SubSuperRegister(unsigned, MVT::SimpleValueType, bool High=false); 139 140 //get512BitRegister - X86 utility - returns 512-bit super register 141 unsigned get512BitSuperRegister(unsigned Reg); 142 143 } // End llvm namespace 144 145 #endif 146
