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      1 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the base ARM implementation of TargetRegisterInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef ARMBASEREGISTERINFO_H
     15 #define ARMBASEREGISTERINFO_H
     16 
     17 #include "ARM.h"
     18 #include "llvm/Target/TargetRegisterInfo.h"
     19 
     20 #define GET_REGINFO_HEADER
     21 #include "ARMGenRegisterInfo.inc"
     22 
     23 namespace llvm {
     24   class ARMSubtarget;
     25   class ARMBaseInstrInfo;
     26   class Type;
     27 
     28 /// Register allocation hints.
     29 namespace ARMRI {
     30   enum {
     31     RegPairOdd  = 1,
     32     RegPairEven = 2
     33   };
     34 }
     35 
     36 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
     37 /// or a stack/pc register that we should push/pop.
     38 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
     39   using namespace ARM;
     40   switch (Reg) {
     41     case R0:  case R1:  case R2:  case R3:
     42     case R4:  case R5:  case R6:  case R7:
     43     case LR:  case SP:  case PC:
     44       return true;
     45     case R8:  case R9:  case R10: case R11:
     46       // For iOS we want r7 and lr to be next to each other.
     47       return !isIOS;
     48     default:
     49       return false;
     50   }
     51 }
     52 
     53 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
     54   using namespace ARM;
     55   switch (Reg) {
     56     case R8: case R9: case R10: case R11:
     57       // iOS has this second area.
     58       return isIOS;
     59     default:
     60       return false;
     61   }
     62 }
     63 
     64 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
     65   using namespace ARM;
     66   switch (Reg) {
     67     case D15: case D14: case D13: case D12:
     68     case D11: case D10: case D9:  case D8:
     69       return true;
     70     default:
     71       return false;
     72   }
     73 }
     74 
     75 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
     76 protected:
     77   const ARMSubtarget &STI;
     78 
     79   /// FramePtr - ARM physical register used as frame ptr.
     80   unsigned FramePtr;
     81 
     82   /// BasePtr - ARM physical register used as a base ptr in complex stack
     83   /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
     84   /// variable size stack objects.
     85   unsigned BasePtr;
     86 
     87   // Can be only subclassed.
     88   explicit ARMBaseRegisterInfo(const ARMSubtarget &STI);
     89 
     90   // Return the opcode that implements 'Op', or 0 if no opcode
     91   unsigned getOpcode(int Op) const;
     92 
     93 public:
     94   /// Code Generation virtual methods...
     95   const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
     96   const uint32_t *getCallPreservedMask(CallingConv::ID) const;
     97   const uint32_t *getNoPreservedMask() const;
     98 
     99   /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
    100   /// case that 'returned' is on an i32 first argument if the calling convention
    101   /// is one that can (partially) model this attribute with a preserved mask
    102   /// (i.e. it is a calling convention that uses the same register for the first
    103   /// i32 argument and an i32 return value)
    104   ///
    105   /// Should return NULL in the case that the calling convention does not have
    106   /// this property
    107   const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
    108 
    109   BitVector getReservedRegs(const MachineFunction &MF) const;
    110 
    111   const TargetRegisterClass*
    112   getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
    113   const TargetRegisterClass*
    114   getCrossCopyRegClass(const TargetRegisterClass *RC) const;
    115 
    116   const TargetRegisterClass*
    117   getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
    118 
    119   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
    120                                MachineFunction &MF) const;
    121 
    122   void getRegAllocationHints(unsigned VirtReg,
    123                              ArrayRef<MCPhysReg> Order,
    124                              SmallVectorImpl<MCPhysReg> &Hints,
    125                              const MachineFunction &MF,
    126                              const VirtRegMap *VRM) const;
    127 
    128   void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
    129                           MachineFunction &MF) const;
    130 
    131   virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
    132 
    133   bool hasBasePointer(const MachineFunction &MF) const;
    134 
    135   bool canRealignStack(const MachineFunction &MF) const;
    136   bool needsStackRealignment(const MachineFunction &MF) const;
    137   int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
    138   bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
    139   void materializeFrameBaseRegister(MachineBasicBlock *MBB,
    140                                     unsigned BaseReg, int FrameIdx,
    141                                     int64_t Offset) const;
    142   void resolveFrameIndex(MachineBasicBlock::iterator I,
    143                          unsigned BaseReg, int64_t Offset) const;
    144   bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
    145 
    146   bool cannotEliminateFrame(const MachineFunction &MF) const;
    147 
    148   // Debug information queries.
    149   unsigned getFrameRegister(const MachineFunction &MF) const;
    150   unsigned getBaseRegister() const { return BasePtr; }
    151 
    152   // Exception handling queries.
    153   unsigned getEHExceptionRegister() const;
    154   unsigned getEHHandlerRegister() const;
    155 
    156   bool isLowRegister(unsigned Reg) const;
    157 
    158 
    159   /// emitLoadConstPool - Emits a load from constpool to materialize the
    160   /// specified immediate.
    161   virtual void emitLoadConstPool(MachineBasicBlock &MBB,
    162                                  MachineBasicBlock::iterator &MBBI,
    163                                  DebugLoc dl,
    164                                  unsigned DestReg, unsigned SubIdx,
    165                                  int Val,
    166                                  ARMCC::CondCodes Pred = ARMCC::AL,
    167                                  unsigned PredReg = 0,
    168                                  unsigned MIFlags = MachineInstr::NoFlags)const;
    169 
    170   /// Code Generation virtual methods...
    171   virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
    172 
    173   virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
    174 
    175   virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
    176 
    177   virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
    178 
    179   virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
    180                                    int SPAdj, unsigned FIOperandNum,
    181                                    RegScavenger *RS = NULL) const;
    182 };
    183 
    184 } // end namespace llvm
    185 
    186 #endif
    187