| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
98 addOffset(const MachineInstrBuilder &MIB, int Offset) {
99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
107 addRegOffset(const MachineInstrBuilder &MIB,
109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
114 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
122 addFullAddress(const MachineInstrBuilder &MIB,
127 MIB.addReg(AM.Base.Reg)
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 25 /// Add a BDX memory reference for frame object FI to MIB.
27 addFrameReference(const MachineInstrBuilder &MIB, int FI) {
28 MachineInstr *MI = MIB;
43 return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO);
|
| SystemZFrameLowering.cpp | 106 // Add GPR64 to the save instruction being built by MIB, which is in basic
110 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
117 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
176 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
179 addSavedGPR(MBB, MIB, TM, LowGPR, false);
180 addSavedGPR(MBB, MIB, TM, HighGPR, false);
183 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
190 addSavedGPR(MBB, MIB, TM, Reg, true);
196 addSavedGPR(MBB, MIB, TM, SystemZ::ArgGPRs[I], true);
246 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG))
[all...] |
| SystemZInstrInfo.cpp | 489 MachineInstrBuilder MIB =
493 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
496 MIB.addOperand(MI->getOperand(I));
497 return finishConvertToThreeAddress(MI, MIB, LV);
524 MachineInstrBuilder MIB =
529 return finishConvertToThreeAddress(MI, MIB, LV);
615 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(MemOpcode));
617 MIB.addOperand(MI->getOperand(I));
618 MIB.addFrameIndex(FrameIndex).addImm(Offset);
620 MIB.addReg(0)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
417 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| Thumb1FrameLowering.cpp | 320 MachineInstrBuilder MIB =
323 AddDefaultPred(MIB);
324 MIB.copyImplicitOps(&*MBBI);
344 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
345 AddDefaultPred(MIB);
363 MIB.addReg(Reg, getKillRegState(isKill));
365 MIB.setMIFlags(MachineInstr::FrameSetup);
383 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
384 AddDefaultPred(MIB);
394 (*MIB).setDesc(TII.get(ARM::tPOP_RET))
[all...] |
| ARMBaseInstrInfo.cpp | 672 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
673 MIB.addReg(SrcReg, getKillRegState(KillSrc));
675 MIB.addReg(SrcReg, getKillRegState(KillSrc));
676 AddDefaultPred(MIB);
745 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
749 return MIB.addReg(Reg, State);
752 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
753 return MIB.addReg(Reg, State, SubIdx);
793 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
794 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI)
[all...] |
| Thumb2SizeReduction.cpp | 496 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
498 MIB.addOperand(MI->getOperand(0));
499 MIB.addOperand(MI->getOperand(1));
502 MIB.addImm(OffsetImm / Scale);
507 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
512 MIB.addOperand(MI->getOperand(OpNum));
515 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
518 MIB.setMIFlags(MI->getFlags());
520 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
556 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc()
[all...] |
| ARMBaseInstrInfo.h | 138 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
322 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
323 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
327 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
328 return MIB.addReg(0);
332 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
334 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
338 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
339 return MIB.addReg(0);
|
| Thumb1RegisterInfo.cpp | 130 MachineInstrBuilder MIB =
133 MIB = AddDefaultT1CC(MIB);
135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
138 AddDefaultPred(MIB);
242 const MachineInstrBuilder MIB =
245 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
263 MIB = AddDefaultT1CC(MIB)
[all...] |
| Thumb2InstrInfo.cpp | 157 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
158 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
159 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
160 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
161 AddDefaultPred(MIB);
198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
201 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
202 AddDefaultPred(MIB);
[all...] |
| ARMInstrInfo.cpp | 126 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
130 MIB.addImm(0);
131 AddDefaultPred(MIB);
|
| ARMFastISel.cpp | 225 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
227 const MachineInstrBuilder &MIB,
273 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
274 MachineInstr *MI = &*MIB;
280 AddDefaultPred(MIB);
287 AddDefaultT1CC(MIB);
289 AddDefaultCC(MIB);
291 return MIB;
678 MachineInstrBuilder MIB;
681 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg
[all...] |
| MLxExpansionPass.cpp | 292 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
296 MIB.addImm(LaneImm);
297 MIB.addImm(Pred).addReg(PredReg);
299 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
304 MIB.addReg(TmpReg, getKillRegState(true))
307 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
309 MIB.addImm(Pred).addReg(PredReg);
|
| ARMFrameLowering.cpp | 224 MachineInstrBuilder MIB =
228 AddDefaultCC(AddDefaultPred(MIB));
449 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
451 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
455 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
460 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
630 MachineInstrBuilder MIB =
634 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
636 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
641 AddDefaultPred(MIB);
[all...] |
| Thumb2ITBlockPass.cpp | 181 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
189 MachineBasicBlock::iterator InsertPos = MIB;
232 MIB.addImm(Mask);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 207 MachineInstrBuilder &MIB,
226 MIB.addReg(VRBase, RegState::Define);
241 MIB.addReg(VRBase, RegState::Define);
253 MIB.addReg(VRBase, RegState::Define);
295 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
308 const MCInstrDesc &MCID = MIB->getDesc();
340 unsigned Idx = MIB->getNumOperands();
342 MIB->getOperand(Idx-1).isReg() &&
343 MIB->getOperand(Idx-1).isImplicit())
350 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill)
[all...] |
| InstrEmitter.h | 53 MachineInstrBuilder &MIB,
66 void AddRegisterOperand(MachineInstrBuilder &MIB,
77 void AddOperand(MachineInstrBuilder &MIB,
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 100 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
104 MIB.addReg(Cond[i].getReg());
106 MIB.addImm(Cond[i].getImm());
110 MIB.addMBB(TBB);
280 MachineInstrBuilder MIB;
281 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
284 MIB.addOperand(I->getOperand(J));
286 MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
287 return MIB;
|
| MipsSEISelDAGToDAG.cpp | 46 MachineInstrBuilder MIB(MF, &MI);
51 MIB.addReg(Mips::DSPPos, Flag);
54 MIB.addReg(Mips::DSPSCount, Flag);
57 MIB.addReg(Mips::DSPCarry, Flag);
60 MIB.addReg(Mips::DSPOutFlag, Flag);
63 MIB.addReg(Mips::DSPCCond, Flag);
66 MIB.addReg(Mips::DSPEFI, Flag);
|
| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.cpp | 83 MachineInstrBuilder MIB(*MF, MI);
84 MIB.addReg(DstReg, RegState::Define);
85 MIB.addReg(AMDGPU::ALU_LITERAL_X);
86 MIB.addImm(Imm);
87 MIB.addReg(0); // PREDICATE_BIT
948 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
949 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 110 MachineInstrBuilder MIB = BuildMI(*MBB.getParent(), FirstMI->getDebugLoc(),
112 Bundle.prepend(MIB);
191 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
200 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 214 MachineInstrBuilder MIB;
216 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_Bimm));
218 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
222 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
229 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_BRx));
230 MIB.addReg(JumpTarget.getReg(), RegState::Kill);
236 MIB->addOperand(MBBI->getOperand(i));
|
