| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 252 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
264 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
270 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
279 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
358 unsigned Op1, Op2;
359 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
363 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
371 unsigned Op1, Op2;
372 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
376 Inst.addOperand(MCOperand::CreateImm(Op1));
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 160 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS))
161 if (Op1->getOpcode() == OpcodeToExpand) {
163 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1);
198 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS);
201 !Op1 || Op1->getOpcode() != OpcodeToExtract)
206 Value *C = Op1->getOperand(0), *D = Op1->getOperand(1);
269 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)
[all...] |
| ConstantFolding.cpp | 540 /// SymbolicallyEvaluateBinop - One of Op0/Op1 is a constant expression.
545 Constant *Op1, const DataLayout *DL){
558 ComputeMaskedBits(Op1, KnownZero1, KnownOne1, DL);
564 // All the bits of Op1 that the 'and' could be masking are already zero.
565 return Op1;
584 if (IsConstantOffsetFromGlobal(Op1, GV2, Offs2, *DL) &&
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 119 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
121 if (Value *V = SimplifyMulInst(Op0, Op1, TD))
127 if (match(Op1, m_AllOnes())) // X * -1 == 0 - X
160 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
195 if (isa<Constant>(Op1)) {
207 if (Value *Op1v = dyn_castNegVal(Op1))
213 Value *Op1C = Op1;
219 BO = dyn_cast<BinaryOperator>(Op1);
251 return BinaryOperator::CreateAnd(Op0, Op1);
258 return BinaryOperator::CreateShl(Op1, Y)
[all...] |
| InstCombineShifts.cpp | 24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
32 if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
36 if (ConstantInt *CUI = dyn_cast<ConstantInt>(Op1))
44 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) {
48 Op1->getName());
312 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1,
320 CanEvaluateShifted(Op0, Op1->getZExtValue(), isLeftShift, *this)) {
325 GetShiftedValue(Op0, Op1->getZExtValue(), isLeftShift, *this));
336 if (Op1->uge(TypeBits))
[all...] |
| InstCombineCompares.cpp | [all...] |
| InstCombineAddSub.cpp | [all...] |
| InstCombineAndOrXor.cpp | 710 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1);
713 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder);
[all...] |
| InstructionCombining.cpp | 214 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(I.getOperand(1));
247 if (Op1 && Op1->getOpcode() == Opcode) {
249 Value *B = Op1->getOperand(0);
250 Value *C = Op1->getOperand(1);
289 if (Op1 && Op1->getOpcode() == Opcode) {
291 Value *B = Op1->getOperand(0);
292 Value *C = Op1->getOperand(1);
310 if (Op0 && Op1 &
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2,
76 SDValue Op1, SDValue Op2,
92 SDValue Op1, SDValue Op2,
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 60 SDValue Op1, SDValue Op2,
|
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 199 unsigned Op1, bool Op1IsKill);
226 unsigned Op1, bool Op1IsKill,
270 unsigned Op1, bool Op1IsKill);
277 unsigned Op1, bool Op1IsKill,
305 unsigned Op1, bool Op1IsKill,
313 unsigned Op1, bool Op1IsKill,
|
| SelectionDAG.h | 526 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
531 Ops.push_back(Op1);
[all...] |
| ISDOpcodes.h | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 198 SDValue Op0, Op1;
202 if (!SelectADDRrr(Op, Op0, Op1))
203 SelectADDRri(Op, Op0, Op1);
208 OutOps.push_back(Op1);
|
| /external/llvm/lib/Transforms/Scalar/ |
| CorrelatedValuePropagation.cpp | 168 Constant *Op1 = dyn_cast<Constant>(C->getOperand(1));
169 if (!Op1) return false;
175 C->getOperand(0), Op1, *PI, C->getParent());
181 C->getOperand(0), Op1, *PI, C->getParent());
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 580 SDValue Op1 = Op.getOperand(1);
584 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
602 assert(MaskTy.getSizeInBits() == Op1.getValueType().getSizeInBits()
619 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
626 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
628 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
658 SDValue Op1 = Op.getOperand(1);
680 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits()
[all...] |
| FastISel.cpp | 382 unsigned Op1 = getRegForValue(I->getOperand(1));
383 if (Op1 == 0) return false;
387 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
443 unsigned Op1 = getRegForValue(I->getOperand(1));
444 if (Op1 == 0)
454 Op1, Op1IsKill);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 363 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects
364 // between the base and index. Try to fold Op1 into AM's displacement.
366 SDValue Op0, ConstantSDNode *Op1) {
368 int64_t TestDisp = AM.Disp + Op1->getSExtValue();
390 SDValue Op1 = N.getOperand(1);
393 unsigned Op1Code = Op1->getOpcode();
396 return expandAdjDynAlloc(AM, IsBase, Op1);
401 return expandDisp(AM, IsBase, Op1, cast<ConstantSDNode>(Op0));
403 return expandDisp(AM, IsBase, Op0, cast<ConstantSDNode>(Op1));
405 if (IsBase && expandIndex(AM, Op0, Op1))
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| InstructionSimplify.h | 128 Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW,
135 Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact,
142 Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact,
|
| /external/llvm/lib/Target/X86/ |
| X86FloatingPoint.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 153 ICToken Op1 = OperandStack.pop_back_val();
159 Val = Op1.second + Op2.second;
163 Val = Op1.second - Op2.second;
167 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
169 Val = Op1.second * Op2.second;
173 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
176 Val = Op1.second / Op2.second;
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 402 SDValue Op1 = N->getOperand(1);
407 CurDAG->ComputeMaskedBits(Op1, RKZ, RKO);
414 unsigned Op1Opc = Op1.getOpcode();
424 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
425 Op1.getOperand(0).getOpcode() != ISD::SRL) {
426 std::swap(Op0, Op1);
432 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
433 Op1.getOperand(0).getOpcode() != ISD::SRL) {
434 std::swap(Op0, Op1);
445 isInt32Immediate(Op1.getOperand(1), Value))
[all...] |
| /external/llvm/lib/DebugInfo/ |
| DWARFDebugFrame.cpp | 110 uint64_t Op1 = Opcode & DWARF_CFI_PRIMARY_OPERAND_MASK;
115 addInstruction(Primary, Op1);
118 addInstruction(Primary, Op1, Data.getULEB128(Offset));
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 430 SDValue Op1 = N->getOperand(1);
490 if (SelectDirectAddr(Op1, Addr)) {
543 ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset)
544 : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
597 ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
598 : SelectADDRri(Op1.getNode(), Op1, Base, Offset))
[all...] |
