| /external/llvm/utils/TableGen/ |
| AsmWriterInst.h | 11 // the string into operands, which can be literal strings (the constant bits of
12 // the string), actual operands (i.e., operands from the MachineInstr), and
87 std::vector<AsmWriterOperand> Operands;
104 if (!Operands.empty() &&
105 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
106 Operands.back().Str.append(Str);
108 Operands.push_back(AsmWriterOperand(Str));
|
| FastISelEmitter.cpp | 72 /// types. It has utility methods for emitting text based on the operands.
116 SmallVector<OpKind, 3> Operands;
119 return Operands < O.Operands;
122 return Operands == O.Operands;
125 bool empty() const { return Operands.empty(); }
128 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
129 if (Operands[i].isImm() && Operands[i].getImmCode() != 0
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| AsmWriterInst.cpp | 87 Operands.push_back(
119 Operands.push_back(
196 Operands.push_back(AsmWriterOperand("PrintSpecial",
202 unsigned OpNo = CGI.Operands.getOperandNamed(VarName);
203 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo];
206 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName,
213 Operands.push_back(AsmWriterOperand("return;",
222 if (Operands.size() != Other.Operands.size()) return ~1;
225 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
[all...] |
| PseudoLoweringEmitter.cpp | 88 // Normal operands should always have the same type, or we have a
92 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
96 Insn.Operands[BaseIdx + i].Rec->getName() + "'");
100 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
102 OpsAdded += Insn.Operands[i].MINumOperands;
108 // Just add the operands recursively. This is almost certainly
145 if (Insn.Operands.size() != Dag->getNumArgs())
150 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
151 NumMIOperands += Insn.Operands[i].MINumOperands;
157 // If there are more operands that weren't in the DAG, they have t
[all...] |
| InstrInfoEmitter.cpp | 63 std::map<std::string, unsigned> &Operands,
90 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
91 // Handle aggregate operands and normal operands the same way by expanding
92 // either case into a list of operands for this op.
96 // registers in their multi-operand operands. It may also be an anonymous
99 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
103 OperandList.push_back(Inst.Operands[i]);
105 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
106 OperandList.push_back(Inst.Operands[i])
[all...] |
| AsmWriterEmitter.cpp | 65 // Check to see if any other operands are identical in this list, and if so,
108 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
111 O << " " << FirstInst.Operands[i].getCode();
119 FirstInst.Operands[i]));
125 AWI.Operands[i]));
155 if (Inst->Operands.empty())
158 Command = " " + Inst->Operands[0].getCode() + "\n";
193 // If this instruction has no more operands, we isn't anything to merge
197 if (!FirstInst || FirstInst->Operands.size() == Op)
203 // Keep track of the maximum, number of operands or an
[all...] |
| CodeEmitterGen.cpp | 128 // operand number. Non-matching operands are assumed to be in
131 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
133 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
134 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
137 unsigned NumberOps = CGI.Operands.size();
141 CGI.Operands.isFlatOperandNotEmitted(NumberedOp))
147 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
148 std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName;
154 // sub-operands, if there are more than one, so only
219 // operands to the instruction
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| CodeGenInstruction.cpp | 88 // If we have MIOpInfo, then we have #operands equal to number of entries
292 : TheDef(R), Operands(R), InferredFrom(0) {
306 isPredicable = Operands.isPredicable || R->getValueAsBit("isPredicable");
335 ParseConstraints(R->getValueAsString("Constraints"), Operands);
338 Operands.ProcessDisableEncoding(R->getValueAsString("DisableEncoding"));
432 // For register operands, the source register class can be a subclass
473 // Handle "zero_reg" for optional def operands.
477 // Tied operands where the source is a sub-operand of a complex operand
478 // need to represent both operands in the alias destination instruction.
480 // the MC representation of things doesn't use tied operands at all
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| /dalvik/vm/compiler/codegen/x86/libenc/ |
| encoder.inl | 62 inline static void add_r(EncoderBase::Operands & args, const R_Opnd & r, Opnd_Size sz, OpndExt ext = OpndExt_None) {
73 inline static void add_m(EncoderBase::Operands & args, const M_Opnd & m, Opnd_Size sz, OpndExt ext = OpndExt_None) {
80 inline static void add_rm(EncoderBase::Operands & args, const RM_Opnd & rm, Opnd_Size sz, OpndExt ext = OpndExt_None) {
84 inline static void add_xmm(EncoderBase::Operands & args, const XMM_Opnd & xmm, bool dbl) {
94 inline static void add_fp(EncoderBase::Operands & args, unsigned i, bool dbl) {
98 inline static void add_imm(EncoderBase::Operands & args, const Imm_Opnd & imm) {
111 EncoderBase::Operands args;
117 EncoderBase::Operands args;
128 EncoderBase::Operands args;
135 EncoderBase::Operands args
[all...] |
| enc_base.h | 63 class Operands;
70 * @param opnds - operands for the instruction
73 static char * encode(char * stream, Mnemonic mn, const Operands& opnds);
173 * @brief Description of operands' roles in instruction.
177 * @brief Total number of operands in the operation.
191 * A bit-packed info about operands' roles. Each operand's role is
207 * The order of operands is left-to-right, i.e. for MOV, it
217 * @brief Info about single opcode - its opcode bytes, operands,
218 * operands' roles.
236 * @brief Info about opcode's operands
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| enc_wrapper.cpp | 45 inline void add_r(EncoderBase::Operands & args, int physicalReg, OpndSize sz, OpndExt ext = OpndExt_None) {
52 inline void add_m(EncoderBase::Operands & args, int baseReg, int disp, OpndSize sz, OpndExt ext = OpndExt_None) {
58 inline void add_m_scale(EncoderBase::Operands & args, int baseReg, int indexReg, int scale,
65 inline void add_m_disp_scale(EncoderBase::Operands & args, int baseReg, int disp, int indexReg, int scale,
73 inline void add_fp(EncoderBase::Operands & args, unsigned i, bool dbl) {
76 inline void add_imm(EncoderBase::Operands & args, OpndSize sz, int value, bool is_signed) {
113 //TODO: the order of operands
127 printOperand(decInst.operands[decInst.argc-1-k]);
131 void printOperands(EncoderBase::Operands& opnds) {
142 void printEncoderInst(Mnemonic m, EncoderBase::Operands& opnds)
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 31 /// MCOperand - Instances of this class represent operands of the MCInst class.
153 SmallVector<MCOperand, 8> Operands;
163 const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
164 MCOperand &getOperand(unsigned i) { return Operands[i]; }
165 unsigned getNumOperands() const { return Operands.size(); }
168 Operands.push_back(Op);
171 void clear() { Operands.clear(); }
172 size_t size() { return Operands.size(); }
175 iterator begin() { return Operands.begin(); }
176 iterator end() { return Operands.end();
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| MCTargetAsmParser.h | 125 /// \param Operands [out] - The list of parsed operands, this returns
130 SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0;
148 /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
156 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
176 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0;
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 87 // Length is the operand length for D(L,B)-style operands, otherwise
163 // Token operands
172 // Register operands.
184 // Access register operands. Access registers aren't exposed to LLVM
190 // Immediate operands.
202 // Memory operands.
230 assert(N == 1 && "Invalid number of operands");
234 assert(N == 1 && "Invalid number of operands");
239 assert(N == 1 && "Invalid number of operands");
243 assert(N == 2 && "Invalid number of operands");
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 69 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
76 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
84 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
92 ParseNEONLane(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
96 ParseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
100 ParseImmWithLSLOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
103 ParseCondCodeOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
106 ParseCRxOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
109 ParseFPImmOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
112 ParseNamedImmOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 71 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
79 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
84 parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
88 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
91 parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
94 parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
97 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
100 parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
103 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
106 parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| ScalarEvolutionExpressions.h | 139 const SCEV *const *Operands;
144 : SCEV(ID, T), Operands(O), NumOperands(N) {}
150 return Operands[i];
154 op_iterator op_begin() const { return Operands; }
155 op_iterator op_end() const { return Operands + NumOperands; }
281 /// All operands of an AddRec are required to be loop invariant.
293 const SCEV *getStart() const { return Operands[0]; }
581 SmallVector<const SCEV *, 2> Operands;
583 Operands.push_back(visit(Expr->getOperand(i)));
584 return SE.getAddExpr(Operands);
[all...] |
| ConstantFolding.h | 11 // operands are constants, for example "sub i32 1, 0" -> "1".
36 /// Note that this fails if not all of the operands are constant. Otherwise,
50 /// specified operands. If successful, the constant result is returned, if not,
61 /// instruction (icmp/fcmp) with the specified operands. If it fails, it
62 /// returns a constant expression of the specified operands.
70 /// instruction with the specified operands and indices. The constant result is
98 Constant *ConstantFoldCall(Function *F, ArrayRef<Constant *> Operands,
|
| /external/llvm/lib/Analysis/ |
| ScalarEvolutionNormalization.cpp | 109 SmallVector<const SCEV *, 8> Operands;
111 // The addrec conceptually uses its operands at loop entry.
116 Operands.push_back(TransformSubExpr(*I, LUser, 0));
119 const SCEV *Result = SE.getAddRecExpr(Operands, L, SCEV::FlagAnyWrap);
160 SmallVector<const SCEV *, 8> Operands;
168 Operands.push_back(N);
173 case scAddExpr: return SE.getAddExpr(Operands);
174 case scMulExpr: return SE.getMulExpr(Operands);
175 case scSMaxExpr: return SE.getSMaxExpr(Operands);
176 case scUMaxExpr: return SE.getUMaxExpr(Operands);
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 150 assert (OperandStack.size() > 1 && "Too few operands.");
524 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
568 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
863 assert(N == 1 && "Invalid number of operands!");
868 assert(N == 1 && "Invalid number of operands!");
917 assert((N == 5) && "Invalid number of operands!");
926 assert((N == 1) && "Invalid number of operands!");
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 229 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
231 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
270 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
277 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
[all...] |
| /external/llvm/lib/Transforms/IPO/ |
| ArgumentPromotion.cpp | 21 // more than three operands to the function, because passing thousands of
22 // operands for a large array or structure is unprofitable! This limit can be
259 // This load is safe if any prefix of its operands is safe to load.
372 IndicesVector Operands;
376 Operands.clear();
382 Operands.push_back(0);
399 Operands.push_back(C->getSExtValue());
419 // is safe if Operands, or a prefix of Operands, is marked as safe.
420 if (!PrefixIn(Operands, SafeToUnconditionallyLoad)
[all...] |
| /external/llvm/test/MC/X86/ |
| x86_operands.s | 30 # Indirect Memory Operands
|
| /external/llvm/lib/CodeGen/ |
| MachineInstr.cpp | 216 // Register operands don't have target flags.
530 /// implicit operands. It reserves space for the number of operands specified by
534 : MCID(&tid), Parent(0), Operands(0), NumOperands(0),
537 // Reserve space for the expected number of operands.
541 Operands = MF.allocateOperandArray(CapOperands);
551 : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0),
556 Operands = MF.allocateOperandArray(CapOperands);
558 // Copy operands.
575 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands i
[all...] |
| /external/llvm/lib/IR/ |
| Metadata.cpp | 52 // Use CallbackVH to hold MDNode operands.
124 // Mark the first MDNodeOperand as being the first in the list of operands.
141 // Destroy the operands.
187 // critical code because it recursively visits all the MDNode's operands.
220 // isFunctionLocal bit because that's implied by the operands.
221 // Note that if the operands are later nulled out, the node will be
253 // Coallocate space for the node and Operands together, then placement new.
312 // isFunctionLocal bit because that's implied by the operands.
313 // Note that if the operands are later nulled out, the node will be
353 // If this node is already not being uniqued (because one of the operands
[all...] |
