| /dalvik/vm/compiler/codegen/mips/ |
| CodegenCommon.cpp | 183 if (flags & REG_DEF_LR) {
249 if (flags & REG_DEF_LR) {
|
| GlobalOptimizations.cpp | 110 if (EncodingMap[nextLIR->opcode].flags & REG_DEF_LR ||
|
| MipsLIR.h | 525 #define REG_DEF_LR (1 << kRegDefLR)
|
| Assemble.cpp | 107 kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH | REG_DEF_LR,
153 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR,
[all...] |
| /dalvik/vm/compiler/codegen/arm/ |
| CodegenCommon.cpp | 165 if (flags & REG_DEF_LR) {
241 if (flags & REG_DEF_LR) {
|
| ArmLIR.h | 681 #define REG_DEF_LR (1 << kRegDefLR)
[all...] |
| Assemble.cpp | 162 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_DEF_LR,
166 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_DEF_LR,
170 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR,
174 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR,
179 IS_UNARY_OP | REG_USE0 | IS_BRANCH | REG_DEF_LR,
[all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 161 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_DEF_LR |
165 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_DEF_LR |
169 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR,
173 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR,
178 IS_UNARY_OP | REG_USE0 | IS_BRANCH | REG_DEF_LR,
404 REG_DEF_LR | NEEDS_FIXUP, "vldr", "!0s, [!1C, #!2E]", 4),
408 REG_DEF_LR | NEEDS_FIXUP, "vldr", "!0S, [!1C, #!2E]", 4),
[all...] |
| target_arm.cc | 191 if (flags & REG_DEF_LR) {
|
| /art/compiler/dex/quick/mips/ |
| assemble_mips.cc | 111 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR |
157 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR,
411 kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH | REG_DEF_LR,
[all...] |
| target_mips.cc | 137 if (flags & REG_DEF_LR) {
|
| /art/compiler/dex/quick/ |
| mir_to_lir.h | 56 #define REG_DEF_LR (1ULL << kRegDefLR)
[all...] |
