| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | 50 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
53 static void executeFAddInst(GenericValue &Dest, GenericValue Src1,
64 static void executeFSubInst(GenericValue &Dest, GenericValue Src1,
75 static void executeFMulInst(GenericValue &Dest, GenericValue Src1,
86 static void executeFDivInst(GenericValue &Dest, GenericValue Src1,
97 static void executeFRemInst(GenericValue &Dest, GenericValue Src1,
101 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal);
104 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal);
114 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
119 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size());
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 98 unsigned Src1 = 0;
102 Src1 = MI.getOperand(2).getReg();
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
153 .addReg(Src1)
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 98 unsigned Src1 = 0;
102 Src1 = MI.getOperand(2).getReg();
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
153 .addReg(Src1)
|
| /external/llvm/lib/Target/R600/ |
| R600ExpandSpecialInstrs.cpp | 82 AMDGPU::ZERO); // src1
198 unsigned Src1 = BMI->getOperand(
199 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
202 (void) Src1;
204 (TRI.getEncodingValue(Src1) & 0xff) < 127)
205 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
249 unsigned Src1 = 0;
253 int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1);
255 Src1 = MI.getOperand(Src1Idx).getReg();
261 Src1 = TRI.getSubReg(Src1, SubRegIndex)
[all...] |
| R600InstrInfo.cpp | 195 AMDGPU::OpName::src1,
207 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
261 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
484 //Todo : support shared src0 - src1 operand
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 159 MachineOperand &Src1 = MI->getOperand(1);
161 if (Src1.getImm() != 0)
176 MachineOperand &Src1 = MI->getOperand(1);
181 unsigned SrcReg = Src1.getReg();
|
| HexagonISelDAGToDAG.cpp | 730 // def STrid : STInst<(outs), (ins MEMri:$addr, DoubleRegs:$src1), ...
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/api/ |
| armCOMM_IDCT_s.h | 664 Src1 EQU 8
674 qXj1 QN Src1.S16
685 dXj1lo DN (Src1*2).S16
686 dXj1hi DN (Src1*2+1).S16
877 XTR6 EQU Src1
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/ |
| armCOMM_IDCT_s.h | 670 Src1 EQU 8
680 qXj1 QN Src1.S16
691 dXj1lo DN (Src1*2).S16
692 dXj1hi DN (Src1*2+1).S16
883 XTR6 EQU Src1
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | [all...] |
| LegalizeVectorTypes.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
