| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 142 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
144 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
147 .addReg(TmpReg)
170 unsigned TmpReg = createResultReg(RC);
172 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
176 .addReg(TmpReg).addImm(Lo);
|
| PPCFrameLowering.cpp | 885 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
895 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
897 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
898 .addReg(TmpReg, RegState::Kill)
903 .addReg(TmpReg);
[all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 289 unsigned TmpReg = MRI->createVirtualRegister(
292 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
304 MIB.addReg(TmpReg, getKillRegState(true))
307 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
|
| Thumb1RegisterInfo.cpp | 634 unsigned TmpReg = MI.getOperand(0).getReg();
638 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
641 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
645 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
650 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 204 unsigned BaseReg, IndexReg, TmpReg, Scale;
213 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
249 BaseReg = TmpReg;
252 IndexReg = TmpReg;
285 BaseReg = TmpReg;
288 IndexReg = TmpReg;
305 TmpReg = Reg;
355 IndexReg = TmpReg;
426 BaseReg = TmpReg;
429 IndexReg = TmpReg;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 408 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
417 TmpReg = getRegisterInfo().getSubReg(DstReg, SubIdx);
422 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
423 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
