| /art/compiler/dex/quick/ |
| local_optimizations.cc | 24 #define CHECK_REG_DEP(use, def, check) ((def & check->use_mask) || \
110 uint64_t this_mem_mask = (this_lir->use_mask | this_lir->def_mask) & ENCODE_MEM;
123 stop_use_reg_mask = (IS_BRANCH | this_lir->use_mask) & ~ENCODE_MEM;
131 stop_use_reg_mask = (GetPCUseDefEncoding() | this_lir->use_mask) & ~ENCODE_MEM;
143 uint64_t check_mem_mask = (check_lir->use_mask | check_lir->def_mask) & ENCODE_MEM;
301 uint64_t stop_use_all_mask = this_lir->use_mask;
440 if (((cur_lir->use_mask & prev_lir->def_mask) && prev_is_load) || (slot < LD_LATENCY)) {
|
| mir_to_lir-inl.h | 56 insn->use_mask = insn->def_mask = ENCODE_ALL;
140 lir->use_mask = lir->def_mask = 0;
164 lir->def_mask = lir->use_mask = ENCODE_ALL;
186 SetupRegMask(&lir->use_mask, lir->operands[i]);
192 lir->use_mask |= ENCODE_CCODE;
|
| codegen_util.cc | 68 mask_ptr = &lir->use_mask;
193 if (lir->use_mask && (!lir->flags.is_nop || dump_nop)) {
194 DUMP_RESOURCE_MASK(DumpResourceMask(lir, lir->use_mask, "use"));
[all...] |
| mir_to_lir.h | 126 uint64_t use_mask; // Resource mask for use. member in struct:art::LIR
[all...] |
| /external/libnfc-nci/src/nfa/ce/ |
| nfa_ce_api.c | 404 tNFA_TECHNOLOGY_MASK use_mask = (NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B); local
407 if (((tech_mask & use_mask) == 0) ||
408 ((tech_mask & ~use_mask) != 0) )
|
| /art/compiler/dex/quick/arm/ |
| target_arm.cc | 133 lir->use_mask |= ENCODE_ARM_REG_SP;
155 lir->use_mask |= ENCODE_ARM_REG_PC;
164 lir->use_mask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
168 lir->use_mask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
172 lir->use_mask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
177 SetupRegMask(&lir->use_mask, lir->operands[1] + i);
183 if ((opcode == kThumbPush) && (lir->use_mask & r8Mask)) {
184 lir->use_mask &= ~r8Mask;
185 lir->use_mask |= ENCODE_ARM_REG_LR;
|
| /art/compiler/dex/quick/x86/ |
| target_x86.cc | 142 lir->use_mask |= ENCODE_X86_REG_SP;
157 SetupRegMask(&lir->use_mask, rAX);
161 SetupRegMask(&lir->use_mask, rCX);
165 SetupRegMask(&lir->use_mask, rDX);
|
| /external/valgrind/main/callgrind/ |
| sim.c | 620 * use_mask |= line_start_mask[5] && line_end_mask[8]
683 UInt use_mask; \
692 use_mask = L.line_start_mask[a & L.line_size_mask] & \
701 L.use[idx].mask |= use_mask; \
704 use_mask, L.use[idx].mask, L.use[idx].count); \
718 L.use[idx].mask |= use_mask; \
721 use_mask, L.use[idx].mask, L.use[idx].count); \
734 use_mask, a &~ L.line_size_mask); \
741 use_mask = L.line_start_mask[a & L.line_size_mask]; \
745 L.use[idx].mask |= use_mask; \
[all...] |
| /external/chromium_org/third_party/mesa/src/src/glsl/ |
| linker.cpp | 1406 const unsigned use_mask = (1 << slots) - 1; local
1456 const unsigned use_mask = (1 << to_assign[i].slots) - 1; local
[all...] |
| /external/mesa3d/src/glsl/ |
| linker.cpp | 1406 const unsigned use_mask = (1 << slots) - 1; local
1456 const unsigned use_mask = (1 << to_assign[i].slots) - 1; local
[all...] |
| /art/compiler/dex/quick/mips/ |
| target_mips.cc | 134 lir->use_mask |= ENCODE_MIPS_REG_SP;
|
