| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 64 v4i1 = 14, // 4 x i1 enumerator in enum:llvm::MVT::SimpleValueType
263 case v4i1 :
323 case v4i1:
361 case v4i1: return 4;
486 if (NumElements == 4) return MVT::v4i1;
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 416 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
420 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
429 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
433 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
442 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 8 },
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 132 case MVT::v4i1: return "v4i1";
195 case MVT::v4i1: return VectorType::get(Type::getInt1Ty(Context), 4);
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 244 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
245 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
407 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 73 case MVT::v4i1: return "MVT::v4i1";
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 38 addRegisterClass(MVT::v4i1, &AMDGPU::VReg_128RegClass);
79 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 55 case MVT::v4i1:
[all...] |
