HomeSort by relevance Sort by last modified time
    Searched full:r600 (Results 26 - 50 of 365) sorted by null

12 3 4 5 6 7 8 91011>>

  /external/llvm/test/CodeGen/R600/
fmad.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
6 %r0 = call float @llvm.R600.load.input(i32 0)
7 %r1 = call float @llvm.R600.load.input(i32 1)
8 %r2 = call float @llvm.R600.load.input(i32 2)
15 declare float @llvm.R600.load.input(i32) readnone
llvm.AMDGPU.trunc.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
2 ; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
4 ; R600-CHECK: @amdgpu_trunc
5 ; R600-CHECK: TRUNC * T{{[0-9]+\.[XYZW]}}, KC0[2].Z
r600-encoding.ll 1 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
2 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600-CHECK %s
4 ; The earliest R600 GPUs have a slightly different encoding than the rest of
10 ; R600-CHECK: @test
11 ; R600-CHECK: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}]
15 %0 = call float @llvm.R600.load.input(i32 0)
16 %1 = call float @llvm.R600.load.input(i32 1)
22 declare float @llvm.R600.load.input(i32) readnone
rotr.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood -o - | FileCheck --check-prefix=R600-CHECK %s
2 ; RUN: llc < %s -march=r600 -mcpu=SI -o - | FileCheck --check-prefix=SI-CHECK %s
4 ; R600-CHECK: @rotr
5 ; R600-CHECK: BIT_ALIGN_INT
19 ; R600-CHECK: @rotl
20 ; R600-CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x
21 ; R600-CHECK-NEXT: 32
22 ; R600-CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}}
floor.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
6 %r0 = call float @llvm.R600.load.input(i32 0)
12 declare float @llvm.R600.load.input(i32) readnone
reciprocal.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
6 %r0 = call float @llvm.R600.load.input(i32 0)
12 declare float @llvm.R600.load.input(i32) readnone
texture-input-merge.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
6 %1 = call float @llvm.R600.load.input(i32 0)
7 %2 = call float @llvm.R600.load.input(i32 1)
8 %3 = call float @llvm.R600.load.input(i32 2)
9 %4 = call float @llvm.R600.load.input(i32 3)
19 %14 = call <4 x float> @llvm.R600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
20 %15 = call <4 x float> @llvm.R600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
21 %16 = call <4 x float> @llvm.R600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
24 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0)
28 declare float @llvm.R600.load.input(i32) readnon
    [all...]
fmax.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
6 %r0 = call float @llvm.R600.load.input(i32 0)
7 %r1 = call float @llvm.R600.load.input(i32 1)
14 declare float @llvm.R600.load.input(i32) readnone
fmin.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
6 %r0 = call float @llvm.R600.load.input(i32 0)
7 %r1 = call float @llvm.R600.load.input(i32 1)
14 declare float @llvm.R600.load.input(i32) readnone
llvm.AMDGPU.mul.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
6 %r0 = call float @llvm.R600.load.input(i32 0)
7 %r1 = call float @llvm.R600.load.input(i32 1)
13 declare float @llvm.R600.load.input(i32) readnone
load.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK %s
3 ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s
10 ; R600-CHECK: @load_i8
11 ; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
22 ; R600-CHECK: @load_i8_sext
23 ; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
24 ; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]
    [all...]
fabs.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
2 ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
8 ; R600-CHECK: @fabs_free
9 ; R600-CHECK-NOT: AND
10 ; R600-CHECK: |PV.{{[XYZW]}}|
max-literals.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
8 %0 = call float @llvm.R600.load.input(i32 4)
9 %1 = call float @llvm.R600.load.input(i32 5)
10 %2 = call float @llvm.R600.load.input(i32 6)
11 %3 = call float @llvm.R600.load.input(i32 7)
12 %4 = call float @llvm.R600.load.input(i32 8)
28 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2)
37 %0 = call float @llvm.R600.load.input(i32 4)
38 %1 = call float @llvm.R600.load.input(i32 5)
39 %2 = call float @llvm.R600.load.input(i32 6
    [all...]
bfi_int.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
2 ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s
7 ; R600-CHECK: @bfi_def
8 ; R600-CHECK: BFI_INT
23 ; R600-CHECK: @bfi_sha256_ch
24 ; R600-CHECK: BFI_INT
38 ; R600-CHECK: @bfi_sha256_ma
39 ; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W
40 ; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].
    [all...]
pv-packing.ll 1 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s
8 %0 = call float @llvm.R600.load.input(i32 4)
9 %1 = call float @llvm.R600.load.input(i32 5)
10 %2 = call float @llvm.R600.load.input(i32 6)
11 %3 = call float @llvm.R600.load.input(i32 8)
12 %4 = call float @llvm.R600.load.input(i32 9)
13 %5 = call float @llvm.R600.load.input(i32 10)
14 %6 = call float @llvm.R600.load.input(i32 12)
15 %7 = call float @llvm.R600.load.input(i32 13)
16 %8 = call float @llvm.R600.load.input(i32 14
    [all...]
llvm.AMDGPU.barrier.local.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
7 %0 = call i32 @llvm.r600.read.tidig.x()
11 %2 = call i32 @llvm.r600.read.local.size.x()
20 declare i32 @llvm.r600.read.tidig.x() #0
22 declare i32 @llvm.r600.read.local.size.x() #0
cf_end.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood --show-mc-encoding | FileCheck --check-prefix=EG-CHECK %s
2 ; RUN: llc < %s -march=r600 -mcpu=caicos --show-mc-encoding | FileCheck --check-prefix=EG-CHECK %s
3 ; RUN: llc < %s -march=r600 -mcpu=cayman --show-mc-encoding | FileCheck --check-prefix=CM-CHECK %s
llvm.cos.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
9 %r0 = call float @llvm.R600.load.input(i32 0)
17 declare float @llvm.R600.load.input(i32) readnone
llvm.sin.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
9 %r0 = call float @llvm.R600.load.input(i32 0)
17 declare float @llvm.R600.load.input(i32) readnone
lit.local.cfg 11 if not 'R600' in targets:
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeonsi/
r600_resource.c 55 void r600_init_context_resource_functions(struct r600_context *r600)
57 r600->context.get_transfer = u_get_transfer_vtbl;
58 r600->context.transfer_map = u_transfer_map_vtbl;
59 r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
60 r600->context.transfer_unmap = u_transfer_unmap_vtbl;
61 r600->context.transfer_destroy = u_transfer_destroy_vtbl;
62 r600->context.transfer_inline_write = u_default_transfer_inline_write;
  /external/mesa3d/src/gallium/drivers/radeonsi/
r600_resource.c 55 void r600_init_context_resource_functions(struct r600_context *r600)
57 r600->context.get_transfer = u_get_transfer_vtbl;
58 r600->context.transfer_map = u_transfer_map_vtbl;
59 r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
60 r600->context.transfer_unmap = u_transfer_unmap_vtbl;
61 r600->context.transfer_destroy = u_transfer_destroy_vtbl;
62 r600->context.transfer_inline_write = u_default_transfer_inline_write;
  /external/clang/test/Driver/
r600-mcpu.cl 3 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=r600 %s -o - 2>&1 | FileCheck --check-prefix=R600-CHECK %s
4 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv630 %s -o - 2>&1 | FileCheck --check-prefix=R600-CHECK %s
5 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv635 %s -o - 2>&1 | FileCheck --check-prefix=R600-CHECK %s
6 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv610 %s -o - 2>&1 | FileCheck --check-prefix=RS880-CHECK %s
7 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv620 %s -o - 2>&1 | FileCheck --check-prefix=RS880-CHECK %s
8 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rs780 %s -o - 2>&1 | FileCheck --check-prefix=RS880-CHECK %
    [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/targets/dri-r600/
target.c 4 #include "r600/r600_public.h"
40 DRM_DRIVER_DESCRIPTOR("r600", "radeon", create_screen, drm_configuration)
  /external/mesa3d/src/gallium/targets/dri-r600/
target.c 4 #include "r600/r600_public.h"
40 DRM_DRIVER_DESCRIPTOR("r600", "radeon", create_screen, drm_configuration)

Completed in 258 milliseconds

12 3 4 5 6 7 8 91011>>