| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 273 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
274 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
275 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
276 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
279 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
280 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
281 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
[all...] |
| ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32;
|
| ARMTargetTransformInfo.cpp | 201 EVT SrcTy = TLI->getValueType(Src);
202 EVT DstTy = TLI->getValueType(Dst);
412 EVT SelCondTy = TLI->getValueType(CondTy);
413 EVT SelValTy = TLI->getValueType(ValTy);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 277 EVT VT = Op.getValueType();
357 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
377 EVT VT = Op.getValueType();
390 EVT VT = Op.getValueType();
401 EVT CompareVT = LHS.getValueType();
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 277 EVT VT = Op.getValueType();
357 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
377 EVT VT = Op.getValueType();
390 EVT VT = Op.getValueType();
401 EVT CompareVT = LHS.getValueType();
|
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 78 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
80 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
82 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM,
84 bool X86FastEmitStore(EVT VT, unsigned ValReg, const X86AddressMode &AM,
87 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
136 bool isScalarFPTypeInSSEReg(EVT VT) const {
152 EVT evt = TLI.getValueType(Ty, /*HandleUnknown=*/true); local
153 if (evt == MVT::Other || !evt.isSimple()
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 529 EVT VT = Op.getValueType();
741 EVT VT = Op.getValueType();
779 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
821 EVT VT = Op.getValueType();
831 EVT CompareVT = LHS.getValueType();
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 340 EVT RegVT = VA.getLocVT();
386 << EVT(VA.getLocVT()).getEVTString()
630 EVT VT = Op.getValueType();
[all...] |
| MSP430ISelDAGToDAG.cpp | 255 EVT VT = N.getValueType();
308 EVT VT = LD->getMemoryVT();
|
| /frameworks/compile/slang/ |
| slang_rs_reflection.cpp | 178 const RSExportVectorType *EVT =
181 VecName << EVT->getRSReflectionType(EVT)->rs_java_vector_prefix
182 << EVT->getNumElement();
240 const RSExportVectorType *EVT = static_cast<const RSExportVectorType*>(ET);
241 if (EVT->getType() == RSExportPrimitiveType::DataTypeFloat32) {
242 if (EVT->getNumElement() == 2)
244 else if (EVT->getNumElement() == 3)
246 else if (EVT->getNumElement() == 4)
248 } else if (EVT->getType() == RSExportPrimitiveType::DataTypeUnsigned8)
[all...] |
| slang_rs_export_type.h | 379 // @EVT was normalized by calling RSExportType::NormalizeType() before
382 const clang::ExtVectorType *EVT,
390 static llvm::StringRef GetTypeName(const clang::ExtVectorType *EVT);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 298 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 29 static bool is32Bit(EVT VT) {
259 SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
278 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
283 bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
597 EVT LocVT = VA.getLocVT();
636 EVT PtrVT = getPointerTy();
706 EVT PtrVT = getPointerTy();
[all...] |
| SystemZSelectionDAGInfo.cpp | 68 EVT DstVT = Dst.getValueType();
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 74 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
|
| /external/llvm/utils/TableGen/ |
| IntrinsicEmitter.cpp | 269 if (EVT(VT).isInteger()) {
270 unsigned BitWidth = EVT(VT).getSizeInBits();
349 if (EVT(VT).isVector()) {
350 EVT VVT = VT;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 601 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
645 EVT VT;
855 EVT RegVT = VA.getLocVT();
[all...] |
| HexagonInstrInfo.h | 159 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
|
| /external/llvm/lib/CodeGen/ |
| Analysis.cpp | 75 SmallVectorImpl<EVT> &ValueVTs,
101 // Base case: we can get an EVT for this LLVM IR type.
208 TLI.isTypeLegal(EVT::getEVT(T1)) && TLI.isTypeLegal(EVT::getEVT(T2)));
|
| TargetRegisterInfo.cpp | 103 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 227 EVT VT = LHS.getValueType();
240 EVT ValTy = Addr.getValueType();
405 EVT PtrVT = getTargetLowering()->getPointerTy();
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXGenericToNVVM.cpp | 172 EVT ExtendedGVType = EVT::getEVT(GVType->getElementType(), true);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 223 EVT VT = N->getValueType(i);
231 EVT VT = Op.getNode()->getValueType(Op.getResNo());
433 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
574 EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
|
| ScheduleDAGSDNodes.cpp | 136 SmallVectorImpl<EVT> &VTs,
163 SmallVector<EVT, 4> VTs;
195 SmallVector<EVT, 4> VTs;
464 EVT OpVT = N->getOperand(i).getValueType();
[all...] |
| SelectionDAGPrinter.cpp | 93 EVT VT = Op.getValueType();
|
