| /external/llvm/lib/Target/ARM/ |
| ARMInstrThumb.td | 197 // t_addrmode_is4 := reg + imm5 * 4
209 // t_addrmode_is2 := reg + imm5 * 2
221 // t_addrmode_is1 := reg + imm5
572 // Loads: reg/reg and reg/imm5
584 def i : // reg/imm5
590 // Stores: reg/reg and reg/imm5
601 def i : // reg/imm5
896 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
898 "asr", "\t$Rd, $Rm, $imm5",
899 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMInstrFormats.td | [all...] |
| ARMInstrInfo.td | 499 // {4-0} imm5 shift amount.
500 // asr #32 encoded as imm5 == 0.
[all...] |
| /dalvik/vm/compiler/codegen/arm/armv5te/ |
| ArchVariant.cpp | 83 * EA is calculated by doing "Rn + imm5 << 2". Make sure that the last
|
| /dalvik/vm/compiler/codegen/arm/armv5te-vfp/ |
| ArchVariant.cpp | 83 * EA is calculated by doing "Rn + imm5 << 2". Make sure that the last
|
| /dalvik/vm/compiler/codegen/arm/armv7-a/ |
| ArchVariant.cpp | 78 * EA is calculated by doing "Rn + imm5 << 2". Make sure that the last
|
| /dalvik/vm/compiler/codegen/arm/armv7-a-neon/ |
| ArchVariant.cpp | 78 * EA is calculated by doing "Rn + imm5 << 2". Make sure that the last
|
| /dalvik/vm/compiler/codegen/mips/mips/ |
| ArchVariant.cpp | 81 * EA is calculated by doing "Rn + imm5 << 2", make sure that the last
|
| /art/runtime/ |
| disassembler_arm.cc | 375 uint32_t imm5 = ((imm3 << 3) | imm2) & 0x1F; local
466 bool noShift = (imm5 == 0 && shift_type != 0x3);
474 if (imm5 == 0) {
482 args << StringPrintf(" #%d", imm5);
1057 uint16_t imm5 = (instr >> 6) & 0x1F; local
1067 args << Rd << ", " << rm << ", #" << imm5; local
1205 uint16_t imm5 = (instr >> 6) & 0x1F; local
1223 args << Rt << ", [" << Rn << ", #" << imm5 << "]"; local
1260 uint16_t imm5 = (instr >> 3) & 0x1F; local
1320 uint16_t imm5 = (instr >> 6) & 0x1F; local
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_arm_defs.h | 255 /* --------- Reg or imm5 operands --------- */
258 ARMri5_I5=9, /* imm5, 1 .. 31 only (no zero!) */
268 UInt imm5; member in struct:__anon28988::__anon28989::__anon28990
277 extern ARMRI5* ARMRI5_I5 ( UInt imm5 );
|
| host_mips_defs.h | 272 /* --------- Reg or imm5 operands --------- */
274 MIPSri5_I5 = 7, /* imm5, 1 .. 31 only (no zero!) */
282 UInt imm5; member in struct:__anon29085::__anon29086::__anon29087
290 extern MIPSRI5 *MIPSRI5_I5(UInt imm5);
|
| guest_arm_toIR.c | 8501 UInt regD = 99, regN = 99, regM = 99, imm5 = 99, shift_type = 99; local
8561 UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; local
8619 UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; local
12460 UInt imm5 = INSN(11,7); local
13073 UInt imm5 = (insn >> 7) & 0x1F; \/* 11:7 *\/ local
16251 UInt imm5 = INSN0(10,6); local
16278 UInt imm5 = INSN0(10,6); local
16306 UInt imm5 = INSN0(10,6); local
16453 UInt imm5 = INSN0(10,6); local
16991 UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); local
17071 UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); local
17153 UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); local
17241 UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); local
17282 UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); local
17322 UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); local
[all...] |
| host_arm_defs.c | 492 /* --------- Reg or imm5 operands --------- */
494 ARMRI5* ARMRI5_I5 ( UInt imm5 ) {
497 ri5->ARMri5.I5.imm5 = imm5;
498 vassert(imm5 > 0 && imm5 <= 31); // zero is not allowed
511 vex_printf("%u", ri5->ARMri5.I5.imm5);
2761 UInt imm5 = ri->ARMri5.I5.imm5; local
[all...] |
| /art/compiler/dex/quick/mips/ |
| mips_lir.h | 361 kMipsSra, // sra d,s,imm5 [00000000000] t[20..16] d[15..11] imm5[10..6] [000011].
|
| /dalvik/vm/compiler/codegen/mips/ |
| MipsLIR.h | 454 kMipsSra, /* sra d,s,imm5 [00000000000] t[20..16] d[15..11] imm5[10..6] [000011] */
|
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrFormats.td | 229 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
238 bits<5> imm5;
245 let Inst{4-0} = imm5;
|
| /art/compiler/dex/quick/arm/ |
| arm_lir.h | 341 kThumb2Cbnz, // cbnz rd,<label> [101110] i [1] imm5[7..3] rn[2..0].
342 kThumb2Cbz, // cbn rd,<label> [101100] i [1] imm5[7..3] rn[2..0].
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | [all...] |
| /dalvik/vm/compiler/codegen/arm/ |
| ArmLIR.h | 463 kThumb2Cbnz, /* cbnz rd,<label> [101110] i [1] imm5[7..3]
465 kThumb2Cbz, /* cbn rd,<label> [101100] i [1] imm5[7..3]
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrFormats.td | 547 class A64I_fpimm<bit m, bit s, bits<2> type, bits<5> imm5,
561 let Inst{9-5} = imm5;
|
| /external/chromium_org/v8/src/arm/ |
| assembler-arm.cc | [all...] |
| /external/qemu/ |
| arm-dis.c | 2106 long imm5; local
[all...] |
| mips-dis.c | 908 The RRI format uses RX, RY, and IMM5.
924 The RI64 format uses RY and IMM5.
[all...] |
| /external/valgrind/main/none/tests/arm/ |
| v6intThumb.c | [all...] |
