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  /external/oprofile/module/ia64/
IA64minstate.h 120 * the minimum state necessary that allows us to turn psr.ic back
124 * psr.ic: off
125 * psr.dt: off
129 * psr.ic: off
133 * p15 = TRUE if psr.i is set in cr.ipsr
137 * Note that psr.ic is NOT turned on by this macro. This is so that
154 /* extract psr.cpl */ \
157 /* are we in kernel mode already? (psr.cpl==0) */ \
222 * SAVE_REST saves the remainder of pt_regs (with psr.ic on). This
227 * psr.ic: o
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op_pmu.c 217 __asm__ __volatile__ ("rsm psr.pp;;"::: "memory");
247 /* disable profiling with the psr.pp bit */
278 * On UP kernels, we do not need to constantly set the psr.pp bit
279 * when a task is scheduled. The psr.pp bit can only be changed in
282 * psr.pp from their saved state. There is this no impact on the context switch
302 * update psr.pp
321 /* The default control register pp value is copied into psr.pp
347 __asm__ __volatile__ ("ssm psr.pp;;"::: "memory");
361 __asm__ __volatile__ ("rsm psr.pp;;"::: "memory");
  /external/antlr/antlr-3.4/runtime/C/doxygen/
buildrec.dox 123 /// pLangParser psr;
207 /// psr = LangParserNew(tstream); // CParserNew is generated by ANTLR3
209 /// if (psr == NULL)
234 /// langAST = psr->decl(psr);
240 /// if (psr->pParser->rec->errorCount > 0)
242 /// ANTLR3_FPRINTF(stderr, "The parser returned %d errors, tree walking aborted.\n", psr->pParser->rec->errorCount);
261 /// psr ->free (psr); psr = NULL
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  /cts/suite/cts/utils/
grapher.py 18 import get_csv_report as psr namespace
41 (_, tests) = psr.parseReports(os.path.abspath(argv[1]))
  /external/kernel-headers/original/asm-arm/
ptrace.h 36 * PSR bits
63 * Groups of PSR bits
  /system/core/toolbox/
ps.c 46 int prio, nice, rtprio, sched, psr; local
129 psr = atoi(nexttok(&ptr)); // processor
163 printf(" %-2d", psr);
  /external/elfutils/backends/
sparc_corenote.c 52 GR (32, 1, 65), /* %psr */
sparc_regs.c 61 { "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" }, /* v8 */
ia64_regs.c 125 "vfp", "vrap", "pr", "ip", "psr", "cfm"
  /external/chromium_org/third_party/openssl/openssl/crypto/aes/asm/
aes-ia64.S 288 mov loc0=psr.um
322 { .mii; mov psr.um=loc0
413 { .mfb; mov psr.um=loc0 // restore user mask
667 mov loc0=psr.um
701 { .mii; mov psr.um=loc0
792 { .mfb; mov psr.um=loc0 // restore user mask
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  /external/openssl/crypto/aes/asm/
aes-ia64.S 288 mov loc0=psr.um
322 { .mii; mov psr.um=loc0
413 { .mfb; mov psr.um=loc0 // restore user mask
667 mov loc0=psr.um
701 { .mii; mov psr.um=loc0
792 { .mfb; mov psr.um=loc0 // restore user mask
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  /sdk/emulator/qtools/
thumbdis.cpp 81 %C print the PSR sub type.
107 /* Format 5 instructions do not update the PSR. */
  /system/core/libpixelflinger/codeflinger/
disassem.c 93 * F - PSR transfer fields
465 /* F - PSR transfer fields */
  /external/ganymed-ssh2/src/main/java/ch/ethz/ssh2/channel/
ChannelManager.java 646 PacketSessionX11Request psr; local
653 psr = new PacketSessionX11Request(c.remoteID, true, singleConnection, x11AuthenticationProtocol,
663 tm.sendMessage(psr.getPayload());
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  /external/qemu/target-arm/
translate.c 9860 uint32_t psr; local
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  /external/chromium_org/third_party/openssl/openssl/crypto/md5/asm/
md5-ia64.S 301 rum psr.be;; // switch to little-endian
350 sum psr.be;; // switch back to big-endian mode
  /external/openssl/crypto/md5/asm/
md5-ia64.S 301 rum psr.be;; // switch to little-endian
350 sum psr.be;; // switch back to big-endian mode
  /external/strace/
syscall.c 686 long r8, r10, psr; variable
965 if (upeek (tcp, PT_CR_IPSR, &psr) >= 0)
966 ia32 = (psr & IA64_PSR_IS) != 0;
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defs.h 226 #include <asm/psr.h>
strace.c 2643 long psr = 0; local
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  /external/qemu/distrib/sdl-1.2.15/src/video/
SDL_yuv_mmx.c 369 "psraw $6, %%mm3\n" // psr 6
  /external/qemu/
gdbstub.c 751 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
815 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
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monitor.c     [all...]
  /external/chromium_org/third_party/usb_ids/
usb.ids     [all...]
  /external/elfutils/tests/
run-allregs.sh     [all...]

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