1 /* 2 * Copyright (C) 2006, 2007, 2008, 2009, 2013 Apple Inc. All rights reserved. 3 * Copyright (C) 2007-2009 Torch Mobile, Inc. 4 * Copyright (C) 2010, 2011 Research In Motion Limited. All rights reserved. 5 * Copyright (C) 2013 Samsung Electronics. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY APPLE COMPUTER, INC. ``AS IS'' AND ANY 17 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE COMPUTER, INC. OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 24 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef WTF_CPU_h 30 #define WTF_CPU_h 31 32 #include "wtf/Compiler.h" 33 34 /* CPU() - the target CPU architecture */ 35 #define CPU(WTF_FEATURE) (defined WTF_CPU_##WTF_FEATURE && WTF_CPU_##WTF_FEATURE) 36 37 /* ==== CPU() - the target CPU architecture ==== */ 38 39 /* This also defines CPU(BIG_ENDIAN) or CPU(MIDDLE_ENDIAN) or neither, as appropriate. */ 40 41 /* CPU(ALPHA) - DEC Alpha */ 42 #if defined(__alpha__) 43 #define WTF_CPU_ALPHA 1 44 #endif 45 46 /* CPU(IA64) - Itanium / IA-64 */ 47 #if defined(__ia64__) 48 #define WTF_CPU_IA64 1 49 #endif 50 51 /* CPU(MIPS) - MIPS 32-bit */ 52 /* Note: Only O32 ABI is tested, so we enable it for O32 ABI for now. */ 53 #if (defined(mips) || defined(__mips__) || defined(MIPS) || defined(_MIPS_)) \ 54 && defined(_ABIO32) 55 #define WTF_CPU_MIPS 1 56 #if defined(__MIPSEB__) 57 #define WTF_CPU_BIG_ENDIAN 1 58 #endif 59 /* MIPS requires allocators to use aligned memory */ 60 #define WTF_USE_ARENA_ALLOC_ALIGNMENT_INTEGER 1 61 #endif /* MIPS */ 62 63 /* CPU(PPC) - PowerPC 32-bit */ 64 #if defined(__ppc__) \ 65 || defined(__PPC__) \ 66 || defined(__powerpc__) \ 67 || defined(__powerpc) \ 68 || defined(__POWERPC__) \ 69 || defined(_M_PPC) \ 70 || defined(__PPC) 71 #define WTF_CPU_PPC 1 72 #define WTF_CPU_BIG_ENDIAN 1 73 #endif 74 75 /* CPU(PPC64) - PowerPC 64-bit */ 76 #if defined(__ppc64__) \ 77 || defined(__PPC64__) 78 #define WTF_CPU_PPC64 1 79 #define WTF_CPU_BIG_ENDIAN 1 80 #endif 81 82 /* CPU(SH4) - SuperH SH-4 */ 83 #if defined(__SH4__) 84 #define WTF_CPU_SH4 1 85 #endif 86 87 /* CPU(SPARC32) - SPARC 32-bit */ 88 #if defined(__sparc) && !defined(__arch64__) || defined(__sparcv8) 89 #define WTF_CPU_SPARC32 1 90 #define WTF_CPU_BIG_ENDIAN 1 91 #endif 92 93 /* CPU(SPARC64) - SPARC 64-bit */ 94 #if defined(__sparc__) && defined(__arch64__) || defined (__sparcv9) 95 #define WTF_CPU_SPARC64 1 96 #define WTF_CPU_BIG_ENDIAN 1 97 #endif 98 99 /* CPU(SPARC) - any SPARC, true for CPU(SPARC32) and CPU(SPARC64) */ 100 #if CPU(SPARC32) || CPU(SPARC64) 101 #define WTF_CPU_SPARC 1 102 #endif 103 104 /* CPU(S390X) - S390 64-bit */ 105 #if defined(__s390x__) 106 #define WTF_CPU_S390X 1 107 #define WTF_CPU_BIG_ENDIAN 1 108 #endif 109 110 /* CPU(S390) - S390 32-bit */ 111 #if defined(__s390__) 112 #define WTF_CPU_S390 1 113 #define WTF_CPU_BIG_ENDIAN 1 114 #endif 115 116 /* CPU(X86) - i386 / x86 32-bit */ 117 #if defined(__i386__) \ 118 || defined(i386) \ 119 || defined(_M_IX86) \ 120 || defined(_X86_) \ 121 || defined(__THW_INTEL) 122 #define WTF_CPU_X86 1 123 #endif 124 125 /* CPU(X86_64) - AMD64 / Intel64 / x86_64 64-bit */ 126 #if defined(__x86_64__) \ 127 || defined(_M_X64) 128 #define WTF_CPU_X86_64 1 129 #endif 130 131 /* CPU(ARM) - ARM, any version*/ 132 #define WTF_ARM_ARCH_AT_LEAST(N) (CPU(ARM) && defined(WTF_ARM_ARCH_VERSION) && WTF_ARM_ARCH_VERSION >= N) 133 134 #if defined(arm) \ 135 || defined(__arm__) \ 136 || defined(ARM) \ 137 || defined(_ARM_) 138 #define WTF_CPU_ARM 1 139 140 #if defined(__ARMEB__) 141 #define WTF_CPU_BIG_ENDIAN 1 142 143 #elif !defined(__ARM_EABI__) \ 144 && !defined(__EABI__) \ 145 && !defined(__VFP_FP__) \ 146 && !defined(_WIN32_WCE) \ 147 && !defined(ANDROID) 148 #define WTF_CPU_MIDDLE_ENDIAN 1 149 150 #endif 151 152 /* Set WTF_ARM_ARCH_VERSION */ 153 #if defined(__ARM_ARCH_4__) \ 154 || defined(__ARM_ARCH_4T__) \ 155 || defined(__MARM_ARMV4__) 156 #define WTF_ARM_ARCH_VERSION 4 157 158 #elif defined(__ARM_ARCH_5__) \ 159 || defined(__ARM_ARCH_5T__) \ 160 || defined(__MARM_ARMV5__) 161 #define WTF_ARM_ARCH_VERSION 5 162 163 #elif defined(__ARM_ARCH_5E__) \ 164 || defined(__ARM_ARCH_5TE__) \ 165 || defined(__ARM_ARCH_5TEJ__) 166 #define WTF_ARM_ARCH_VERSION 5 167 /*ARMv5TE requires allocators to use aligned memory*/ 168 #define WTF_USE_ARENA_ALLOC_ALIGNMENT_INTEGER 1 169 170 #elif defined(__ARM_ARCH_6__) \ 171 || defined(__ARM_ARCH_6J__) \ 172 || defined(__ARM_ARCH_6K__) \ 173 || defined(__ARM_ARCH_6Z__) \ 174 || defined(__ARM_ARCH_6ZK__) \ 175 || defined(__ARM_ARCH_6T2__) \ 176 || defined(__ARMV6__) 177 #define WTF_ARM_ARCH_VERSION 6 178 179 #elif defined(__ARM_ARCH_7A__) \ 180 || defined(__ARM_ARCH_7R__) \ 181 || defined(__ARM_ARCH_7S__) 182 #define WTF_ARM_ARCH_VERSION 7 183 184 /* MSVC sets _M_ARM */ 185 #elif defined(_M_ARM) 186 #define WTF_ARM_ARCH_VERSION _M_ARM 187 #else 188 #define WTF_ARM_ARCH_VERSION 0 189 190 #endif 191 192 /* Set WTF_THUMB_ARCH_VERSION */ 193 #if defined(__ARM_ARCH_4T__) 194 #define WTF_THUMB_ARCH_VERSION 1 195 196 #elif defined(__ARM_ARCH_5T__) \ 197 || defined(__ARM_ARCH_5TE__) \ 198 || defined(__ARM_ARCH_5TEJ__) 199 #define WTF_THUMB_ARCH_VERSION 2 200 201 #elif defined(__ARM_ARCH_6J__) \ 202 || defined(__ARM_ARCH_6K__) \ 203 || defined(__ARM_ARCH_6Z__) \ 204 || defined(__ARM_ARCH_6ZK__) \ 205 || defined(__ARM_ARCH_6M__) 206 #define WTF_THUMB_ARCH_VERSION 3 207 208 #elif defined(__ARM_ARCH_6T2__) \ 209 || defined(__ARM_ARCH_7__) \ 210 || defined(__ARM_ARCH_7A__) \ 211 || defined(__ARM_ARCH_7M__) \ 212 || defined(__ARM_ARCH_7R__) \ 213 || defined(__ARM_ARCH_7S__) 214 #define WTF_THUMB_ARCH_VERSION 4 215 216 #else 217 #define WTF_THUMB_ARCH_VERSION 0 218 #endif 219 220 221 /* CPU(ARM_TRADITIONAL) - Thumb2 is not available, only traditional ARM (v4 or greater) */ 222 /* CPU(ARM_THUMB2) - Thumb2 instruction set is available */ 223 /* Only one of these will be defined. */ 224 #if !defined(WTF_CPU_ARM_TRADITIONAL) && !defined(WTF_CPU_ARM_THUMB2) 225 # if defined(thumb2) || defined(__thumb2__) \ 226 || ((defined(__thumb) || defined(__thumb__)) && WTF_THUMB_ARCH_VERSION == 4) 227 # define WTF_CPU_ARM_TRADITIONAL 0 228 # define WTF_CPU_ARM_THUMB2 1 229 # elif WTF_ARM_ARCH_AT_LEAST(4) 230 # define WTF_CPU_ARM_TRADITIONAL 1 231 # define WTF_CPU_ARM_THUMB2 0 232 # else 233 # error "Not supported ARM architecture" 234 # endif 235 #elif CPU(ARM_TRADITIONAL) && CPU(ARM_THUMB2) /* Sanity Check */ 236 # error "Cannot use both of WTF_CPU_ARM_TRADITIONAL and WTF_CPU_ARM_THUMB2 platforms" 237 #endif /* !defined(WTF_CPU_ARM_TRADITIONAL) && !defined(WTF_CPU_ARM_THUMB2) */ 238 239 #if defined(__ARM_NEON__) && !defined(WTF_CPU_ARM_NEON) 240 #define WTF_CPU_ARM_NEON 1 241 #endif 242 243 #if CPU(ARM_NEON) && (!COMPILER(GCC) || GCC_VERSION_AT_LEAST(4, 7, 0)) 244 // All NEON intrinsics usage can be disabled by this macro. 245 #define HAVE_ARM_NEON_INTRINSICS 1 246 #endif 247 248 #if defined(__ARM_ARCH_7S__) 249 #define WTF_CPU_APPLE_ARMV7S 1 250 #endif 251 252 #endif /* ARM */ 253 254 #endif /* WTF_CPU_h */ 255
