1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_TARGET_AARCH64_ISELLOWERING_H 16 #define LLVM_TARGET_AARCH64_ISELLOWERING_H 17 18 #include "Utils/AArch64BaseInfo.h" 19 #include "llvm/CodeGen/CallingConvLower.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/Target/TargetLowering.h" 22 23 24 namespace llvm { 25 namespace AArch64ISD { 26 enum NodeType { 27 // Start the numbering from where ISD NodeType finishes. 28 FIRST_NUMBER = ISD::BUILTIN_OP_END, 29 30 // This is a conditional branch which also notes the flag needed 31 // (eq/sgt/...). A64 puts this information on the branches rather than 32 // compares as LLVM does. 33 BR_CC, 34 35 // A node to be selected to an actual call operation: either BL or BLR in 36 // the absence of tail calls. 37 Call, 38 39 // Indicates a floating-point immediate which fits into the format required 40 // by the FMOV instructions. First (and only) operand is the 8-bit encoded 41 // value of that immediate. 42 FPMOV, 43 44 // Corresponds directly to an EXTR instruction. Operands are an LHS an RHS 45 // and an LSB. 46 EXTR, 47 48 // Wraps a load from the GOT, which should always be performed with a 64-bit 49 // load instruction. This prevents the DAG combiner folding a truncate to 50 // form a smaller memory access. 51 GOTLoad, 52 53 // Performs a bitfield insert. Arguments are: the value being inserted into; 54 // the value being inserted; least significant bit changed; width of the 55 // field. 56 BFI, 57 58 // Simply a convenient node inserted during ISelLowering to represent 59 // procedure return. Will almost certainly be selected to "RET". 60 Ret, 61 62 /// Extracts a field of contiguous bits from the source and sign extends 63 /// them into a single register. Arguments are: source; immr; imms. Note 64 /// these are pre-encoded since DAG matching can't cope with combining LSB 65 /// and Width into these values itself. 66 SBFX, 67 68 /// This is an A64-ification of the standard LLVM SELECT_CC operation. The 69 /// main difference is that it only has the values and an A64 condition, 70 /// which will be produced by a setcc instruction. 71 SELECT_CC, 72 73 /// This serves most of the functions of the LLVM SETCC instruction, for two 74 /// purposes. First, it prevents optimisations from fiddling with the 75 /// compare after we've moved the CondCode information onto the SELECT_CC or 76 /// BR_CC instructions. Second, it gives a legal instruction for the actual 77 /// comparison. 78 /// 79 /// It keeps a record of the condition flags asked for because certain 80 /// instructions are only valid for a subset of condition codes. 81 SETCC, 82 83 // Designates a node which is a tail call: both a call and a return 84 // instruction as far as selction is concerned. It should be selected to an 85 // unconditional branch. Has the usual plethora of call operands, but: 1st 86 // is callee, 2nd is stack adjustment required immediately before branch. 87 TC_RETURN, 88 89 // Designates a call used to support the TLS descriptor ABI. The call itself 90 // will be indirect ("BLR xN") but a relocation-specifier (".tlsdesccall 91 // var") must be attached somehow during code generation. It takes two 92 // operands: the callee and the symbol to be relocated against. 93 TLSDESCCALL, 94 95 // Leaf node which will be lowered to an appropriate MRS to obtain the 96 // thread pointer: TPIDR_EL0. 97 THREAD_POINTER, 98 99 /// Extracts a field of contiguous bits from the source and zero extends 100 /// them into a single register. Arguments are: source; immr; imms. Note 101 /// these are pre-encoded since DAG matching can't cope with combining LSB 102 /// and Width into these values itself. 103 UBFX, 104 105 // Wraps an address which the ISelLowering phase has decided should be 106 // created using the large memory model style: i.e. a sequence of four 107 // movz/movk instructions. 108 WrapperLarge, 109 110 // Wraps an address which the ISelLowering phase has decided should be 111 // created using the small memory model style: i.e. adrp/add or 112 // adrp/mem-op. This exists to prevent bare TargetAddresses which may never 113 // get selected. 114 WrapperSmall, 115 116 // Vector bitwise select 117 NEON_BSL, 118 119 // Vector move immediate 120 NEON_MOVIMM, 121 122 // Vector Move Inverted Immediate 123 NEON_MVNIMM, 124 125 // Vector FP move immediate 126 NEON_FMOVIMM, 127 128 // Vector compare 129 NEON_CMP, 130 131 // Vector compare zero 132 NEON_CMPZ, 133 134 // Vector compare bitwise test 135 NEON_TST 136 }; 137 } 138 139 140 class AArch64Subtarget; 141 class AArch64TargetMachine; 142 143 class AArch64TargetLowering : public TargetLowering { 144 public: 145 explicit AArch64TargetLowering(AArch64TargetMachine &TM); 146 147 const char *getTargetNodeName(unsigned Opcode) const; 148 149 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC) const; 150 151 SDValue LowerFormalArguments(SDValue Chain, 152 CallingConv::ID CallConv, bool isVarArg, 153 const SmallVectorImpl<ISD::InputArg> &Ins, 154 SDLoc dl, SelectionDAG &DAG, 155 SmallVectorImpl<SDValue> &InVals) const; 156 157 SDValue LowerReturn(SDValue Chain, 158 CallingConv::ID CallConv, bool isVarArg, 159 const SmallVectorImpl<ISD::OutputArg> &Outs, 160 const SmallVectorImpl<SDValue> &OutVals, 161 SDLoc dl, SelectionDAG &DAG) const; 162 163 SDValue LowerCall(CallLoweringInfo &CLI, 164 SmallVectorImpl<SDValue> &InVals) const; 165 166 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 167 CallingConv::ID CallConv, bool IsVarArg, 168 const SmallVectorImpl<ISD::InputArg> &Ins, 169 SDLoc dl, SelectionDAG &DAG, 170 SmallVectorImpl<SDValue> &InVals) const; 171 172 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 173 const AArch64Subtarget *ST) const; 174 175 void SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL, 176 SDValue &Chain) const; 177 178 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 179 /// for tail call optimization. Targets which want to do tail call 180 /// optimization should implement this function. 181 bool IsEligibleForTailCallOptimization(SDValue Callee, 182 CallingConv::ID CalleeCC, 183 bool IsVarArg, 184 bool IsCalleeStructRet, 185 bool IsCallerStructRet, 186 const SmallVectorImpl<ISD::OutputArg> &Outs, 187 const SmallVectorImpl<SDValue> &OutVals, 188 const SmallVectorImpl<ISD::InputArg> &Ins, 189 SelectionDAG& DAG) const; 190 191 /// Finds the incoming stack arguments which overlap the given fixed stack 192 /// object and incorporates their load into the current chain. This prevents 193 /// an upcoming store from clobbering the stack argument before it's used. 194 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, 195 MachineFrameInfo *MFI, int ClobberedFI) const; 196 197 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 198 199 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const; 200 201 bool IsTailCallConvention(CallingConv::ID CallCC) const; 202 203 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 204 205 bool isLegalICmpImmediate(int64_t Val) const; 206 SDValue getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, 207 SDValue &A64cc, SelectionDAG &DAG, SDLoc &dl) const; 208 209 virtual MachineBasicBlock * 210 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 211 212 MachineBasicBlock * 213 emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB, 214 unsigned Size, unsigned Opcode) const; 215 216 MachineBasicBlock * 217 emitAtomicBinaryMinMax(MachineInstr *MI, MachineBasicBlock *BB, 218 unsigned Size, unsigned CmpOp, 219 A64CC::CondCodes Cond) const; 220 MachineBasicBlock * 221 emitAtomicCmpSwap(MachineInstr *MI, MachineBasicBlock *BB, 222 unsigned Size) const; 223 224 MachineBasicBlock * 225 EmitF128CSEL(MachineInstr *MI, MachineBasicBlock *MBB) const; 226 227 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 228 SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; 229 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 230 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 231 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 232 SDValue LowerF128ToCall(SDValue Op, SelectionDAG &DAG, 233 RTLIB::Libcall Call) const; 234 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 235 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 236 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, bool IsSigned) const; 237 238 SDValue LowerGlobalAddressELFSmall(SDValue Op, SelectionDAG &DAG) const; 239 SDValue LowerGlobalAddressELFLarge(SDValue Op, SelectionDAG &DAG) const; 240 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 241 242 SDValue LowerTLSDescCall(SDValue SymAddr, SDValue DescAddr, SDLoc DL, 243 SelectionDAG &DAG) const; 244 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 245 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool IsSigned) const; 246 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 247 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 248 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 249 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 250 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 251 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 252 253 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 254 255 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 256 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 257 /// expanded to FMAs when this method returns true, otherwise fmuladd is 258 /// expanded to fmul + fadd. 259 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const; 260 261 ConstraintType getConstraintType(const std::string &Constraint) const; 262 263 ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, 264 const char *Constraint) const; 265 void LowerAsmOperandForConstraint(SDValue Op, 266 std::string &Constraint, 267 std::vector<SDValue> &Ops, 268 SelectionDAG &DAG) const; 269 270 std::pair<unsigned, const TargetRegisterClass*> 271 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; 272 private: 273 const InstrItineraryData *Itins; 274 275 const AArch64Subtarget *getSubtarget() const { 276 return &getTargetMachine().getSubtarget<AArch64Subtarget>(); 277 } 278 }; 279 enum NeonModImmType { 280 Neon_Mov_Imm, 281 Neon_Mvn_Imm 282 }; 283 } // namespace llvm 284 285 #endif // LLVM_TARGET_AARCH64_ISELLOWERING_H 286
