1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains instruction defs that are common to all hw codegen 11 // targets. 12 // 13 //===----------------------------------------------------------------------===// 14 15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction { 16 field bit isRegisterLoad = 0; 17 field bit isRegisterStore = 0; 18 19 let Namespace = "AMDGPU"; 20 let OutOperandList = outs; 21 let InOperandList = ins; 22 let AsmString = asm; 23 let Pattern = pattern; 24 let Itinerary = NullALU; 25 26 let TSFlags{63} = isRegisterLoad; 27 let TSFlags{62} = isRegisterStore; 28 } 29 30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern> 31 : AMDGPUInst<outs, ins, asm, pattern> { 32 33 field bits<32> Inst = 0xffffffff; 34 35 } 36 37 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>; 38 39 def COND_EQ : PatLeaf < 40 (cond), 41 [{switch(N->get()){{default: return false; 42 case ISD::SETOEQ: case ISD::SETUEQ: 43 case ISD::SETEQ: return true;}}}] 44 >; 45 46 def COND_NE : PatLeaf < 47 (cond), 48 [{switch(N->get()){{default: return false; 49 case ISD::SETONE: case ISD::SETUNE: 50 case ISD::SETNE: return true;}}}] 51 >; 52 def COND_GT : PatLeaf < 53 (cond), 54 [{switch(N->get()){{default: return false; 55 case ISD::SETOGT: case ISD::SETUGT: 56 case ISD::SETGT: return true;}}}] 57 >; 58 59 def COND_GE : PatLeaf < 60 (cond), 61 [{switch(N->get()){{default: return false; 62 case ISD::SETOGE: case ISD::SETUGE: 63 case ISD::SETGE: return true;}}}] 64 >; 65 66 def COND_LT : PatLeaf < 67 (cond), 68 [{switch(N->get()){{default: return false; 69 case ISD::SETOLT: case ISD::SETULT: 70 case ISD::SETLT: return true;}}}] 71 >; 72 73 def COND_LE : PatLeaf < 74 (cond), 75 [{switch(N->get()){{default: return false; 76 case ISD::SETOLE: case ISD::SETULE: 77 case ISD::SETLE: return true;}}}] 78 >; 79 80 def COND_NULL : PatLeaf < 81 (cond), 82 [{return false;}] 83 >; 84 85 //===----------------------------------------------------------------------===// 86 // Load/Store Pattern Fragments 87 //===----------------------------------------------------------------------===// 88 89 def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 90 LoadSDNode *L = cast<LoadSDNode>(N); 91 return L->getExtensionType() == ISD::ZEXTLOAD || 92 L->getExtensionType() == ISD::EXTLOAD; 93 }]>; 94 95 def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{ 96 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 97 }]>; 98 99 def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{ 100 return isGlobalLoad(dyn_cast<LoadSDNode>(N)); 101 }]>; 102 103 def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{ 104 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); 105 }]>; 106 107 def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{ 108 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); 109 }]>; 110 111 def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{ 112 return isGlobalLoad(dyn_cast<LoadSDNode>(N)); 113 }]>; 114 115 def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{ 116 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 117 }]>; 118 119 def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{ 120 return isGlobalLoad(dyn_cast<LoadSDNode>(N)); 121 }]>; 122 123 def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{ 124 return isGlobalLoad(dyn_cast<LoadSDNode>(N)); 125 }]>; 126 127 def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{ 128 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); 129 }]>; 130 131 def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{ 132 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); 133 }]>; 134 135 def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{ 136 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 137 }]>; 138 139 def az_extloadi32_global : PatFrag<(ops node:$ptr), 140 (az_extloadi32 node:$ptr), [{ 141 return isGlobalLoad(dyn_cast<LoadSDNode>(N)); 142 }]>; 143 144 def az_extloadi32_constant : PatFrag<(ops node:$ptr), 145 (az_extloadi32 node:$ptr), [{ 146 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); 147 }]>; 148 149 def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 150 return isLocalLoad(dyn_cast<LoadSDNode>(N)); 151 }]>; 152 153 def local_store : PatFrag<(ops node:$val, node:$ptr), 154 (store node:$val, node:$ptr), [{ 155 return isLocalStore(dyn_cast<StoreSDNode>(N)); 156 }]>; 157 158 class Constants { 159 int TWO_PI = 0x40c90fdb; 160 int PI = 0x40490fdb; 161 int TWO_PI_INV = 0x3e22f983; 162 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding 163 } 164 def CONST : Constants; 165 166 def FP_ZERO : PatLeaf < 167 (fpimm), 168 [{return N->getValueAPF().isZero();}] 169 >; 170 171 def FP_ONE : PatLeaf < 172 (fpimm), 173 [{return N->isExactlyValue(1.0);}] 174 >; 175 176 def U24 : ComplexPattern<i32, 1, "SelectU24", [], []>; 177 def I24 : ComplexPattern<i32, 1, "SelectI24", [], []>; 178 179 let isCodeGenOnly = 1, isPseudo = 1 in { 180 181 let usesCustomInserter = 1 in { 182 183 class CLAMP <RegisterClass rc> : AMDGPUShaderInst < 184 (outs rc:$dst), 185 (ins rc:$src0), 186 "CLAMP $dst, $src0", 187 [(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))] 188 >; 189 190 class FABS <RegisterClass rc> : AMDGPUShaderInst < 191 (outs rc:$dst), 192 (ins rc:$src0), 193 "FABS $dst, $src0", 194 [(set f32:$dst, (fabs f32:$src0))] 195 >; 196 197 class FNEG <RegisterClass rc> : AMDGPUShaderInst < 198 (outs rc:$dst), 199 (ins rc:$src0), 200 "FNEG $dst, $src0", 201 [(set f32:$dst, (fneg f32:$src0))] 202 >; 203 204 } // usesCustomInserter = 1 205 206 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass, 207 ComplexPattern addrPat> { 208 def RegisterLoad : AMDGPUShaderInst < 209 (outs dstClass:$dst), 210 (ins addrClass:$addr, i32imm:$chan), 211 "RegisterLoad $dst, $addr", 212 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))] 213 > { 214 let isRegisterLoad = 1; 215 } 216 217 def RegisterStore : AMDGPUShaderInst < 218 (outs), 219 (ins dstClass:$val, addrClass:$addr, i32imm:$chan), 220 "RegisterStore $val, $addr", 221 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))] 222 > { 223 let isRegisterStore = 1; 224 } 225 } 226 227 } // End isCodeGenOnly = 1, isPseudo = 1 228 229 /* Generic helper patterns for intrinsics */ 230 /* -------------------------------------- */ 231 232 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul> 233 : Pat < 234 (fpow f32:$src0, f32:$src1), 235 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0))) 236 >; 237 238 /* Other helper patterns */ 239 /* --------------------- */ 240 241 /* Extract element pattern */ 242 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx, 243 SubRegIndex sub_reg> 244 : Pat< 245 (sub_type (vector_extract vec_type:$src, sub_idx)), 246 (EXTRACT_SUBREG $src, sub_reg) 247 >; 248 249 /* Insert element pattern */ 250 class Insert_Element <ValueType elem_type, ValueType vec_type, 251 int sub_idx, SubRegIndex sub_reg> 252 : Pat < 253 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx), 254 (INSERT_SUBREG $vec, $elem, sub_reg) 255 >; 256 257 // Vector Build pattern 258 class Vector1_Build <ValueType vecType, ValueType elemType, 259 RegisterClass rc> : Pat < 260 (vecType (build_vector elemType:$src)), 261 (vecType (COPY_TO_REGCLASS $src, rc)) 262 >; 263 264 class Vector2_Build <ValueType vecType, ValueType elemType> : Pat < 265 (vecType (build_vector elemType:$sub0, elemType:$sub1)), 266 (INSERT_SUBREG (INSERT_SUBREG 267 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1) 268 >; 269 270 class Vector4_Build <ValueType vecType, ValueType elemType> : Pat < 271 (vecType (build_vector elemType:$x, elemType:$y, elemType:$z, elemType:$w)), 272 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 273 (vecType (IMPLICIT_DEF)), $x, sub0), $y, sub1), $z, sub2), $w, sub3) 274 >; 275 276 class Vector8_Build <ValueType vecType, ValueType elemType> : Pat < 277 (vecType (build_vector elemType:$sub0, elemType:$sub1, 278 elemType:$sub2, elemType:$sub3, 279 elemType:$sub4, elemType:$sub5, 280 elemType:$sub6, elemType:$sub7)), 281 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 282 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 283 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1), 284 $sub2, sub2), $sub3, sub3), 285 $sub4, sub4), $sub5, sub5), 286 $sub6, sub6), $sub7, sub7) 287 >; 288 289 class Vector16_Build <ValueType vecType, ValueType elemType> : Pat < 290 (vecType (build_vector elemType:$sub0, elemType:$sub1, 291 elemType:$sub2, elemType:$sub3, 292 elemType:$sub4, elemType:$sub5, 293 elemType:$sub6, elemType:$sub7, 294 elemType:$sub8, elemType:$sub9, 295 elemType:$sub10, elemType:$sub11, 296 elemType:$sub12, elemType:$sub13, 297 elemType:$sub14, elemType:$sub15)), 298 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 299 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 300 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 301 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 302 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1), 303 $sub2, sub2), $sub3, sub3), 304 $sub4, sub4), $sub5, sub5), 305 $sub6, sub6), $sub7, sub7), 306 $sub8, sub8), $sub9, sub9), 307 $sub10, sub10), $sub11, sub11), 308 $sub12, sub12), $sub13, sub13), 309 $sub14, sub14), $sub15, sub15) 310 >; 311 312 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer 313 // can handle COPY instructions. 314 // bitconvert pattern 315 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat < 316 (dt (bitconvert (st rc:$src0))), 317 (dt rc:$src0) 318 >; 319 320 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer 321 // can handle COPY instructions. 322 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat < 323 (vt (AMDGPUdwordaddr (vt rc:$addr))), 324 (vt rc:$addr) 325 >; 326 327 // BFI_INT patterns 328 329 multiclass BFIPatterns <Instruction BFI_INT> { 330 331 // Definition from ISA doc: 332 // (y & x) | (z & ~x) 333 def : Pat < 334 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))), 335 (BFI_INT $x, $y, $z) 336 >; 337 338 // SHA-256 Ch function 339 // z ^ (x & (y ^ z)) 340 def : Pat < 341 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))), 342 (BFI_INT $x, $y, $z) 343 >; 344 345 } 346 347 // SHA-256 Ma patterns 348 349 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y 350 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat < 351 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))), 352 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y) 353 >; 354 355 // Bitfield extract patterns 356 357 def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>; 358 def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}], 359 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>; 360 361 class BFEPattern <Instruction BFE> : Pat < 362 (and (srl i32:$x, legalshift32:$y), bfemask:$z), 363 (BFE $x, $y, $z) 364 >; 365 366 // rotr pattern 367 class ROTRPattern <Instruction BIT_ALIGN> : Pat < 368 (rotr i32:$src0, i32:$src1), 369 (BIT_ALIGN $src0, $src0, $src1) 370 >; 371 372 // 24-bit arithmetic patterns 373 def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>; 374 375 /* 376 class UMUL24Pattern <Instruction UMUL24> : Pat < 377 (mul U24:$x, U24:$y), 378 (UMUL24 $x, $y) 379 >; 380 */ 381 382 include "R600Instructions.td" 383 384 include "SIInstrInfo.td" 385 386
