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      1 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 /// \file
     11 /// \brief The AMDGPU TargetMachine interface definition for hw codgen targets.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef AMDGPU_TARGET_MACHINE_H
     16 #define AMDGPU_TARGET_MACHINE_H
     17 
     18 #include "AMDGPUFrameLowering.h"
     19 #include "AMDGPUInstrInfo.h"
     20 #include "AMDGPUSubtarget.h"
     21 #include "AMDILIntrinsicInfo.h"
     22 #include "R600ISelLowering.h"
     23 #include "llvm/ADT/OwningPtr.h"
     24 #include "llvm/IR/DataLayout.h"
     25 
     26 namespace llvm {
     27 
     28 class AMDGPUTargetMachine : public LLVMTargetMachine {
     29 
     30   AMDGPUSubtarget Subtarget;
     31   const DataLayout Layout;
     32   AMDGPUFrameLowering FrameLowering;
     33   AMDGPUIntrinsicInfo IntrinsicInfo;
     34   OwningPtr<AMDGPUInstrInfo> InstrInfo;
     35   OwningPtr<AMDGPUTargetLowering> TLInfo;
     36   const InstrItineraryData *InstrItins;
     37 
     38 public:
     39   AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS,
     40                       StringRef CPU, TargetOptions Options, Reloc::Model RM,
     41                       CodeModel::Model CM, CodeGenOpt::Level OL);
     42   ~AMDGPUTargetMachine();
     43   virtual const AMDGPUFrameLowering *getFrameLowering() const {
     44     return &FrameLowering;
     45   }
     46   virtual const AMDGPUIntrinsicInfo *getIntrinsicInfo() const {
     47     return &IntrinsicInfo;
     48   }
     49   virtual const AMDGPUInstrInfo *getInstrInfo() const {
     50     return InstrInfo.get();
     51   }
     52   virtual const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; }
     53   virtual const AMDGPURegisterInfo *getRegisterInfo() const {
     54     return &InstrInfo->getRegisterInfo();
     55   }
     56   virtual AMDGPUTargetLowering *getTargetLowering() const {
     57     return TLInfo.get();
     58   }
     59   virtual const InstrItineraryData *getInstrItineraryData() const {
     60     return InstrItins;
     61   }
     62   virtual const DataLayout *getDataLayout() const { return &Layout; }
     63   virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
     64 
     65   /// \brief Register R600 analysis passes with a pass manager.
     66   virtual void addAnalysisPasses(PassManagerBase &PM);
     67 };
     68 
     69 } // End namespace llvm
     70 
     71 #endif // AMDGPU_TARGET_MACHINE_H
     72