1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief SI DAG Lowering interface definition 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef SIISELLOWERING_H 16 #define SIISELLOWERING_H 17 18 #include "AMDGPUISelLowering.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class SITargetLowering : public AMDGPUTargetLowering { 24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, SDLoc DL, 25 SDValue Chain, unsigned Offset) const; 26 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 27 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const; 28 SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const; 29 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 30 31 bool foldImm(SDValue &Operand, int32_t &Immediate, 32 bool &ScalarSlotUsed) const; 33 const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG, 34 const SDValue &Op) const; 35 bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op, 36 unsigned RegClass) const; 37 void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand, 38 unsigned RegClass, bool &ScalarSlotUsed) const; 39 40 SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const; 41 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 42 MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const; 43 44 public: 45 SITargetLowering(TargetMachine &tm); 46 bool allowsUnalignedMemoryAccesses(EVT VT, bool *IsFast) const; 47 48 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 49 bool isVarArg, 50 const SmallVectorImpl<ISD::InputArg> &Ins, 51 SDLoc DL, SelectionDAG &DAG, 52 SmallVectorImpl<SDValue> &InVals) const; 53 54 virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI, 55 MachineBasicBlock * BB) const; 56 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 57 virtual MVT getScalarShiftAmountTy(EVT VT) const; 58 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 59 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 60 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const; 61 virtual void AdjustInstrPostInstrSelection(MachineInstr *MI, 62 SDNode *Node) const; 63 64 int32_t analyzeImmediate(const SDNode *N) const; 65 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, 66 unsigned Reg, EVT VT) const; 67 }; 68 69 } // End namespace llvm 70 71 #endif //SIISELLOWERING_H 72
