1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s 2 3 define <8 x i8> @movi8b() { 4 ;CHECK: movi {{v[0-31]+}}.8b, #0x8 5 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > 6 } 7 8 define <16 x i8> @movi16b() { 9 ;CHECK: movi {{v[0-31]+}}.16b, #0x8 10 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > 11 } 12 13 define <2 x i32> @movi2s_lsl0() { 14 ;CHECK: movi {{v[0-31]+}}.2s, #0xff 15 ret <2 x i32> < i32 255, i32 255 > 16 } 17 18 define <2 x i32> @movi2s_lsl8() { 19 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, lsl #8 20 ret <2 x i32> < i32 65280, i32 65280 > 21 } 22 23 define <2 x i32> @movi2s_lsl16() { 24 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, lsl #16 25 ret <2 x i32> < i32 16711680, i32 16711680 > 26 27 } 28 29 define <2 x i32> @movi2s_lsl24() { 30 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, lsl #24 31 ret <2 x i32> < i32 4278190080, i32 4278190080 > 32 } 33 34 define <4 x i32> @movi4s_lsl0() { 35 ;CHECK: movi {{v[0-31]+}}.4s, #0xff 36 ret <4 x i32> < i32 255, i32 255, i32 255, i32 255 > 37 } 38 39 define <4 x i32> @movi4s_lsl8() { 40 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, lsl #8 41 ret <4 x i32> < i32 65280, i32 65280, i32 65280, i32 65280 > 42 } 43 44 define <4 x i32> @movi4s_lsl16() { 45 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, lsl #16 46 ret <4 x i32> < i32 16711680, i32 16711680, i32 16711680, i32 16711680 > 47 48 } 49 50 define <4 x i32> @movi4s_lsl24() { 51 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, lsl #24 52 ret <4 x i32> < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080 > 53 } 54 55 define <4 x i16> @movi4h_lsl0() { 56 ;CHECK: movi {{v[0-31]+}}.4h, #0xff 57 ret <4 x i16> < i16 255, i16 255, i16 255, i16 255 > 58 } 59 60 define <4 x i16> @movi4h_lsl8() { 61 ;CHECK: movi {{v[0-31]+}}.4h, #0xff, lsl #8 62 ret <4 x i16> < i16 65280, i16 65280, i16 65280, i16 65280 > 63 } 64 65 define <8 x i16> @movi8h_lsl0() { 66 ;CHECK: movi {{v[0-31]+}}.8h, #0xff 67 ret <8 x i16> < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 > 68 } 69 70 define <8 x i16> @movi8h_lsl8() { 71 ;CHECK: movi {{v[0-31]+}}.8h, #0xff, lsl #8 72 ret <8 x i16> < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 > 73 } 74 75 76 define <2 x i32> @mvni2s_lsl0() { 77 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10 78 ret <2 x i32> < i32 4294967279, i32 4294967279 > 79 } 80 81 define <2 x i32> @mvni2s_lsl8() { 82 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, lsl #8 83 ret <2 x i32> < i32 4294963199, i32 4294963199 > 84 } 85 86 define <2 x i32> @mvni2s_lsl16() { 87 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, lsl #16 88 ret <2 x i32> < i32 4293918719, i32 4293918719 > 89 } 90 91 define <2 x i32> @mvni2s_lsl24() { 92 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, lsl #24 93 ret <2 x i32> < i32 4026531839, i32 4026531839 > 94 } 95 96 define <4 x i32> @mvni4s_lsl0() { 97 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10 98 ret <4 x i32> < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 > 99 } 100 101 define <4 x i32> @mvni4s_lsl8() { 102 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, lsl #8 103 ret <4 x i32> < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 > 104 } 105 106 define <4 x i32> @mvni4s_lsl16() { 107 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, lsl #16 108 ret <4 x i32> < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 > 109 110 } 111 112 define <4 x i32> @mvni4s_lsl24() { 113 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, lsl #24 114 ret <4 x i32> < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839 > 115 } 116 117 118 define <4 x i16> @mvni4h_lsl0() { 119 ;CHECK: mvni {{v[0-31]+}}.4h, #0x10 120 ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 > 121 } 122 123 define <4 x i16> @mvni4h_lsl8() { 124 ;CHECK: mvni {{v[0-31]+}}.4h, #0x10, lsl #8 125 ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 > 126 } 127 128 define <8 x i16> @mvni8h_lsl0() { 129 ;CHECK: mvni {{v[0-31]+}}.8h, #0x10 130 ret <8 x i16> < i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519 > 131 } 132 133 define <8 x i16> @mvni8h_lsl8() { 134 ;CHECK: mvni {{v[0-31]+}}.8h, #0x10, lsl #8 135 ret <8 x i16> < i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439 > 136 } 137 138 139 define <2 x i32> @movi2s_msl8(<2 x i32> %a) { 140 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, msl #8 141 ret <2 x i32> < i32 65535, i32 65535 > 142 } 143 144 define <2 x i32> @movi2s_msl16() { 145 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, msl #16 146 ret <2 x i32> < i32 16777215, i32 16777215 > 147 } 148 149 150 define <4 x i32> @movi4s_msl8() { 151 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, msl #8 152 ret <4 x i32> < i32 65535, i32 65535, i32 65535, i32 65535 > 153 } 154 155 define <4 x i32> @movi4s_msl16() { 156 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, msl #16 157 ret <4 x i32> < i32 16777215, i32 16777215, i32 16777215, i32 16777215 > 158 } 159 160 define <2 x i32> @mvni2s_msl8() { 161 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, msl #8 162 ret <2 x i32> < i32 18446744073709547264, i32 18446744073709547264> 163 } 164 165 define <2 x i32> @mvni2s_msl16() { 166 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, msl #16 167 ret <2 x i32> < i32 18446744073708437504, i32 18446744073708437504> 168 } 169 170 define <4 x i32> @mvni4s_msl8() { 171 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, msl #8 172 ret <4 x i32> < i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264> 173 } 174 175 define <4 x i32> @mvni4s_msl16() { 176 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, msl #16 177 ret <4 x i32> < i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504> 178 } 179 180 define <2 x i64> @movi2d() { 181 ;CHECK: movi {{v[0-31]+}}.2d, #0xff0000ff0000ffff 182 ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 > 183 } 184 185 define <1 x i64> @movid() { 186 ;CHECK: movi {{d[0-31]+}}, #0xff0000ff0000ffff 187 ret <1 x i64> < i64 18374687574888349695 > 188 } 189 190 define <2 x float> @fmov2s() { 191 ;CHECK: fmov {{v[0-31]+}}.2s, #-12.00000000 192 ret <2 x float> < float -1.2e1, float -1.2e1> 193 } 194 195 define <4 x float> @fmov4s() { 196 ;CHECK: fmov {{v[0-31]+}}.4s, #-12.00000000 197 ret <4 x float> < float -1.2e1, float -1.2e1, float -1.2e1, float -1.2e1> 198 } 199 200 define <2 x double> @fmov2d() { 201 ;CHECK: fmov {{v[0-31]+}}.2d, #-12.00000000 202 ret <2 x double> < double -1.2e1, double -1.2e1> 203 } 204 205 206
