1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s 2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s 3 4 ;; These tests should run for all targets 5 6 ;;===-- Basic instruction selection tests ---------------------------------===;; 7 8 9 ;;; f64 10 11 define double @fadd_f64(double %a, double %b) { 12 ; CHECK: add.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}} 13 ; CHECK: ret 14 %ret = fadd double %a, %b 15 ret double %ret 16 } 17 18 define double @fsub_f64(double %a, double %b) { 19 ; CHECK: sub.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}} 20 ; CHECK: ret 21 %ret = fsub double %a, %b 22 ret double %ret 23 } 24 25 define double @fmul_f64(double %a, double %b) { 26 ; CHECK: mul.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}} 27 ; CHECK: ret 28 %ret = fmul double %a, %b 29 ret double %ret 30 } 31 32 define double @fdiv_f64(double %a, double %b) { 33 ; CHECK: div.rn.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}} 34 ; CHECK: ret 35 %ret = fdiv double %a, %b 36 ret double %ret 37 } 38 39 ;; PTX does not have a floating-point rem instruction 40 41 42 ;;; f32 43 44 define float @fadd_f32(float %a, float %b) { 45 ; CHECK: add.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}} 46 ; CHECK: ret 47 %ret = fadd float %a, %b 48 ret float %ret 49 } 50 51 define float @fsub_f32(float %a, float %b) { 52 ; CHECK: sub.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}} 53 ; CHECK: ret 54 %ret = fsub float %a, %b 55 ret float %ret 56 } 57 58 define float @fmul_f32(float %a, float %b) { 59 ; CHECK: mul.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}} 60 ; CHECK: ret 61 %ret = fmul float %a, %b 62 ret float %ret 63 } 64 65 define float @fdiv_f32(float %a, float %b) { 66 ; CHECK: div.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}} 67 ; CHECK: ret 68 %ret = fdiv float %a, %b 69 ret float %ret 70 } 71 72 ;; PTX does not have a floating-point rem instruction 73
