1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s 2 3 ;CHECK: TEX 4 ;CHECK-NEXT: ALU 5 6 define void @test() { 7 %1 = call float @llvm.R600.load.input(i32 0) 8 %2 = call float @llvm.R600.load.input(i32 1) 9 %3 = call float @llvm.R600.load.input(i32 2) 10 %4 = call float @llvm.R600.load.input(i32 3) 11 %5 = insertelement <4 x float> undef, float %1, i32 0 12 %6 = insertelement <4 x float> %5, float %2, i32 1 13 %7 = insertelement <4 x float> %6, float %3, i32 2 14 %8 = insertelement <4 x float> %7, float %4, i32 3 15 %9 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 16 %10 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 17 %11 = fadd <4 x float> %9, %10 18 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 0, i32 0) 19 ret void 20 } 21 22 declare float @llvm.R600.load.input(i32) readnone 23 declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone 24 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) 25
