1 //===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the main function for LLVM's TableGen. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "TableGenBackends.h" // Declares all backends. 15 #include "SetTheory.h" 16 #include "llvm/Support/CommandLine.h" 17 #include "llvm/Support/PrettyStackTrace.h" 18 #include "llvm/Support/Signals.h" 19 #include "llvm/TableGen/Error.h" 20 #include "llvm/TableGen/Main.h" 21 #include "llvm/TableGen/Record.h" 22 23 using namespace llvm; 24 25 enum ActionType { 26 PrintRecords, 27 GenEmitter, 28 GenRegisterInfo, 29 GenInstrInfo, 30 GenAsmWriter, 31 GenAsmMatcher, 32 GenDisassembler, 33 GenPseudoLowering, 34 GenCallingConv, 35 GenDAGISel, 36 GenDFAPacketizer, 37 GenFastISel, 38 GenSubtarget, 39 GenIntrinsic, 40 GenTgtIntrinsic, 41 PrintEnums, 42 PrintSets, 43 GenOptParserDefs, 44 GenCTags 45 }; 46 47 namespace { 48 cl::opt<ActionType> 49 Action(cl::desc("Action to perform:"), 50 cl::values(clEnumValN(PrintRecords, "print-records", 51 "Print all records to stdout (default)"), 52 clEnumValN(GenEmitter, "gen-emitter", 53 "Generate machine code emitter"), 54 clEnumValN(GenRegisterInfo, "gen-register-info", 55 "Generate registers and register classes info"), 56 clEnumValN(GenInstrInfo, "gen-instr-info", 57 "Generate instruction descriptions"), 58 clEnumValN(GenCallingConv, "gen-callingconv", 59 "Generate calling convention descriptions"), 60 clEnumValN(GenAsmWriter, "gen-asm-writer", 61 "Generate assembly writer"), 62 clEnumValN(GenDisassembler, "gen-disassembler", 63 "Generate disassembler"), 64 clEnumValN(GenPseudoLowering, "gen-pseudo-lowering", 65 "Generate pseudo instruction lowering"), 66 clEnumValN(GenAsmMatcher, "gen-asm-matcher", 67 "Generate assembly instruction matcher"), 68 clEnumValN(GenDAGISel, "gen-dag-isel", 69 "Generate a DAG instruction selector"), 70 clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer", 71 "Generate DFA Packetizer for VLIW targets"), 72 clEnumValN(GenFastISel, "gen-fast-isel", 73 "Generate a \"fast\" instruction selector"), 74 clEnumValN(GenSubtarget, "gen-subtarget", 75 "Generate subtarget enumerations"), 76 clEnumValN(GenIntrinsic, "gen-intrinsic", 77 "Generate intrinsic information"), 78 clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", 79 "Generate target intrinsic information"), 80 clEnumValN(PrintEnums, "print-enums", 81 "Print enum values for a class"), 82 clEnumValN(PrintSets, "print-sets", 83 "Print expanded sets for testing DAG exprs"), 84 clEnumValN(GenOptParserDefs, "gen-opt-parser-defs", 85 "Generate option definitions"), 86 clEnumValN(GenCTags, "gen-ctags", 87 "Generate ctags-compatible index"), 88 clEnumValEnd)); 89 90 cl::opt<std::string> 91 Class("class", cl::desc("Print Enum list for this class"), 92 cl::value_desc("class name")); 93 94 bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { 95 switch (Action) { 96 case PrintRecords: 97 OS << Records; // No argument, dump all contents 98 break; 99 case GenEmitter: 100 EmitCodeEmitter(Records, OS); 101 break; 102 case GenRegisterInfo: 103 EmitRegisterInfo(Records, OS); 104 break; 105 case GenInstrInfo: 106 EmitInstrInfo(Records, OS); 107 break; 108 case GenCallingConv: 109 EmitCallingConv(Records, OS); 110 break; 111 case GenAsmWriter: 112 EmitAsmWriter(Records, OS); 113 break; 114 case GenAsmMatcher: 115 EmitAsmMatcher(Records, OS); 116 break; 117 case GenDisassembler: 118 EmitDisassembler(Records, OS); 119 break; 120 case GenPseudoLowering: 121 EmitPseudoLowering(Records, OS); 122 break; 123 case GenDAGISel: 124 EmitDAGISel(Records, OS); 125 break; 126 case GenDFAPacketizer: 127 EmitDFAPacketizer(Records, OS); 128 break; 129 case GenFastISel: 130 EmitFastISel(Records, OS); 131 break; 132 case GenSubtarget: 133 EmitSubtarget(Records, OS); 134 break; 135 case GenIntrinsic: 136 EmitIntrinsics(Records, OS); 137 break; 138 case GenTgtIntrinsic: 139 EmitIntrinsics(Records, OS, true); 140 break; 141 case GenOptParserDefs: 142 EmitOptParser(Records, OS); 143 break; 144 case PrintEnums: 145 { 146 std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class); 147 for (unsigned i = 0, e = Recs.size(); i != e; ++i) 148 OS << Recs[i]->getName() << ", "; 149 OS << "\n"; 150 break; 151 } 152 case PrintSets: 153 { 154 SetTheory Sets; 155 Sets.addFieldExpander("Set", "Elements"); 156 std::vector<Record*> Recs = Records.getAllDerivedDefinitions("Set"); 157 for (unsigned i = 0, e = Recs.size(); i != e; ++i) { 158 OS << Recs[i]->getName() << " = ["; 159 const std::vector<Record*> *Elts = Sets.expand(Recs[i]); 160 assert(Elts && "Couldn't expand Set instance"); 161 for (unsigned ei = 0, ee = Elts->size(); ei != ee; ++ei) 162 OS << ' ' << (*Elts)[ei]->getName(); 163 OS << " ]\n"; 164 } 165 break; 166 } 167 case GenCTags: 168 EmitCTags(Records, OS); 169 break; 170 } 171 172 return false; 173 } 174 } 175 176 int main(int argc, char **argv) { 177 sys::PrintStackTraceOnErrorSignal(); 178 PrettyStackTraceProgram X(argc, argv); 179 cl::ParseCommandLineOptions(argc, argv); 180 181 return TableGenMain(argv[0], &LLVMTableGenMain); 182 } 183
