1 #!/usr/bin/env perl 2 # 3 # ==================================================================== 4 # Written by Andy Polyakov <appro (at] fy.chalmers.se> for the OpenSSL 5 # project. Rights for redistribution and usage in source and binary 6 # forms are granted according to the OpenSSL license. 7 # ==================================================================== 8 # 9 # sha256/512_block procedure for x86_64. 10 # 11 # 40% improvement over compiler-generated code on Opteron. On EM64T 12 # sha256 was observed to run >80% faster and sha512 - >40%. No magical 13 # tricks, just straight implementation... I really wonder why gcc 14 # [being armed with inline assembler] fails to generate as fast code. 15 # The only thing which is cool about this module is that it's very 16 # same instruction sequence used for both SHA-256 and SHA-512. In 17 # former case the instructions operate on 32-bit operands, while in 18 # latter - on 64-bit ones. All I had to do is to get one flavor right, 19 # the other one passed the test right away:-) 20 # 21 # sha256_block runs in ~1005 cycles on Opteron, which gives you 22 # asymptotic performance of 64*1000/1005=63.7MBps times CPU clock 23 # frequency in GHz. sha512_block runs in ~1275 cycles, which results 24 # in 128*1000/1275=100MBps per GHz. Is there room for improvement? 25 # Well, if you compare it to IA-64 implementation, which maintains 26 # X[16] in register bank[!], tends to 4 instructions per CPU clock 27 # cycle and runs in 1003 cycles, 1275 is very good result for 3-way 28 # issue Opteron pipeline and X[16] maintained in memory. So that *if* 29 # there is a way to improve it, *then* the only way would be to try to 30 # offload X[16] updates to SSE unit, but that would require "deeper" 31 # loop unroll, which in turn would naturally cause size blow-up, not 32 # to mention increased complexity! And once again, only *if* it's 33 # actually possible to noticeably improve overall ILP, instruction 34 # level parallelism, on a given CPU implementation in this case. 35 # 36 # Special note on Intel EM64T. While Opteron CPU exhibits perfect 37 # perfromance ratio of 1.5 between 64- and 32-bit flavors [see above], 38 # [currently available] EM64T CPUs apparently are far from it. On the 39 # contrary, 64-bit version, sha512_block, is ~30% *slower* than 32-bit 40 # sha256_block:-( This is presumably because 64-bit shifts/rotates 41 # apparently are not atomic instructions, but implemented in microcode. 42 43 $flavour = shift; 44 $output = shift; 45 if ($flavour =~ /\./) { $output = $flavour; undef $flavour; } 46 47 $win64=0; $win64=1 if ($flavour =~ /[nm]asm|mingw64/ || $output =~ /\.asm$/); 48 49 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1; 50 ( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or 51 ( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or 52 die "can't locate x86_64-xlate.pl"; 53 54 open OUT,"| \"$^X\" $xlate $flavour $output"; 55 *STDOUT=*OUT; 56 57 if ($output =~ /512/) { 58 $func="sha512_block_data_order"; 59 $TABLE="K512"; 60 $SZ=8; 61 @ROT=($A,$B,$C,$D,$E,$F,$G,$H)=("%rax","%rbx","%rcx","%rdx", 62 "%r8", "%r9", "%r10","%r11"); 63 ($T1,$a0,$a1,$a2)=("%r12","%r13","%r14","%r15"); 64 @Sigma0=(28,34,39); 65 @Sigma1=(14,18,41); 66 @sigma0=(1, 8, 7); 67 @sigma1=(19,61, 6); 68 $rounds=80; 69 } else { 70 $func="sha256_block_data_order"; 71 $TABLE="K256"; 72 $SZ=4; 73 @ROT=($A,$B,$C,$D,$E,$F,$G,$H)=("%eax","%ebx","%ecx","%edx", 74 "%r8d","%r9d","%r10d","%r11d"); 75 ($T1,$a0,$a1,$a2)=("%r12d","%r13d","%r14d","%r15d"); 76 @Sigma0=( 2,13,22); 77 @Sigma1=( 6,11,25); 78 @sigma0=( 7,18, 3); 79 @sigma1=(17,19,10); 80 $rounds=64; 81 } 82 83 $ctx="%rdi"; # 1st arg 84 $round="%rdi"; # zaps $ctx 85 $inp="%rsi"; # 2nd arg 86 $Tbl="%rbp"; 87 88 $_ctx="16*$SZ+0*8(%rsp)"; 89 $_inp="16*$SZ+1*8(%rsp)"; 90 $_end="16*$SZ+2*8(%rsp)"; 91 $_rsp="16*$SZ+3*8(%rsp)"; 92 $framesz="16*$SZ+4*8"; 93 94 95 sub ROUND_00_15() 96 { my ($i,$a,$b,$c,$d,$e,$f,$g,$h) = @_; 97 98 $code.=<<___; 99 ror \$`$Sigma1[2]-$Sigma1[1]`,$a0 100 mov $f,$a2 101 mov $T1,`$SZ*($i&0xf)`(%rsp) 102 103 ror \$`$Sigma0[2]-$Sigma0[1]`,$a1 104 xor $e,$a0 105 xor $g,$a2 # f^g 106 107 ror \$`$Sigma1[1]-$Sigma1[0]`,$a0 108 add $h,$T1 # T1+=h 109 xor $a,$a1 110 111 add ($Tbl,$round,$SZ),$T1 # T1+=K[round] 112 and $e,$a2 # (f^g)&e 113 mov $b,$h 114 115 ror \$`$Sigma0[1]-$Sigma0[0]`,$a1 116 xor $e,$a0 117 xor $g,$a2 # Ch(e,f,g)=((f^g)&e)^g 118 119 xor $c,$h # b^c 120 xor $a,$a1 121 add $a2,$T1 # T1+=Ch(e,f,g) 122 mov $b,$a2 123 124 ror \$$Sigma1[0],$a0 # Sigma1(e) 125 and $a,$h # h=(b^c)&a 126 and $c,$a2 # b&c 127 128 ror \$$Sigma0[0],$a1 # Sigma0(a) 129 add $a0,$T1 # T1+=Sigma1(e) 130 add $a2,$h # h+=b&c (completes +=Maj(a,b,c) 131 132 add $T1,$d # d+=T1 133 add $T1,$h # h+=T1 134 lea 1($round),$round # round++ 135 add $a1,$h # h+=Sigma0(a) 136 137 ___ 138 } 139 140 sub ROUND_16_XX() 141 { my ($i,$a,$b,$c,$d,$e,$f,$g,$h) = @_; 142 143 $code.=<<___; 144 mov `$SZ*(($i+1)&0xf)`(%rsp),$a0 145 mov `$SZ*(($i+14)&0xf)`(%rsp),$a1 146 mov $a0,$T1 147 mov $a1,$a2 148 149 ror \$`$sigma0[1]-$sigma0[0]`,$T1 150 xor $a0,$T1 151 shr \$$sigma0[2],$a0 152 153 ror \$$sigma0[0],$T1 154 xor $T1,$a0 # sigma0(X[(i+1)&0xf]) 155 mov `$SZ*(($i+9)&0xf)`(%rsp),$T1 156 157 ror \$`$sigma1[1]-$sigma1[0]`,$a2 158 xor $a1,$a2 159 shr \$$sigma1[2],$a1 160 161 ror \$$sigma1[0],$a2 162 add $a0,$T1 163 xor $a2,$a1 # sigma1(X[(i+14)&0xf]) 164 165 add `$SZ*($i&0xf)`(%rsp),$T1 166 mov $e,$a0 167 add $a1,$T1 168 mov $a,$a1 169 ___ 170 &ROUND_00_15(@_); 171 } 172 173 $code=<<___; 174 .text 175 176 .globl $func 177 .type $func,\@function,4 178 .align 16 179 $func: 180 push %rbx 181 push %rbp 182 push %r12 183 push %r13 184 push %r14 185 push %r15 186 mov %rsp,%r11 # copy %rsp 187 shl \$4,%rdx # num*16 188 sub \$$framesz,%rsp 189 lea ($inp,%rdx,$SZ),%rdx # inp+num*16*$SZ 190 and \$-64,%rsp # align stack frame 191 mov $ctx,$_ctx # save ctx, 1st arg 192 mov $inp,$_inp # save inp, 2nd arh 193 mov %rdx,$_end # save end pointer, "3rd" arg 194 mov %r11,$_rsp # save copy of %rsp 195 .Lprologue: 196 197 lea $TABLE(%rip),$Tbl 198 199 mov $SZ*0($ctx),$A 200 mov $SZ*1($ctx),$B 201 mov $SZ*2($ctx),$C 202 mov $SZ*3($ctx),$D 203 mov $SZ*4($ctx),$E 204 mov $SZ*5($ctx),$F 205 mov $SZ*6($ctx),$G 206 mov $SZ*7($ctx),$H 207 jmp .Lloop 208 209 .align 16 210 .Lloop: 211 xor $round,$round 212 ___ 213 for($i=0;$i<16;$i++) { 214 $code.=" mov $SZ*$i($inp),$T1\n"; 215 $code.=" mov @ROT[4],$a0\n"; 216 $code.=" mov @ROT[0],$a1\n"; 217 $code.=" bswap $T1\n"; 218 &ROUND_00_15($i,@ROT); 219 unshift(@ROT,pop(@ROT)); 220 } 221 $code.=<<___; 222 jmp .Lrounds_16_xx 223 .align 16 224 .Lrounds_16_xx: 225 ___ 226 for(;$i<32;$i++) { 227 &ROUND_16_XX($i,@ROT); 228 unshift(@ROT,pop(@ROT)); 229 } 230 231 $code.=<<___; 232 cmp \$$rounds,$round 233 jb .Lrounds_16_xx 234 235 mov $_ctx,$ctx 236 lea 16*$SZ($inp),$inp 237 238 add $SZ*0($ctx),$A 239 add $SZ*1($ctx),$B 240 add $SZ*2($ctx),$C 241 add $SZ*3($ctx),$D 242 add $SZ*4($ctx),$E 243 add $SZ*5($ctx),$F 244 add $SZ*6($ctx),$G 245 add $SZ*7($ctx),$H 246 247 cmp $_end,$inp 248 249 mov $A,$SZ*0($ctx) 250 mov $B,$SZ*1($ctx) 251 mov $C,$SZ*2($ctx) 252 mov $D,$SZ*3($ctx) 253 mov $E,$SZ*4($ctx) 254 mov $F,$SZ*5($ctx) 255 mov $G,$SZ*6($ctx) 256 mov $H,$SZ*7($ctx) 257 jb .Lloop 258 259 mov $_rsp,%rsi 260 mov (%rsi),%r15 261 mov 8(%rsi),%r14 262 mov 16(%rsi),%r13 263 mov 24(%rsi),%r12 264 mov 32(%rsi),%rbp 265 mov 40(%rsi),%rbx 266 lea 48(%rsi),%rsp 267 .Lepilogue: 268 ret 269 .size $func,.-$func 270 ___ 271 272 if ($SZ==4) { 273 $code.=<<___; 274 .align 64 275 .type $TABLE,\@object 276 $TABLE: 277 .long 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5 278 .long 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5 279 .long 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3 280 .long 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174 281 .long 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc 282 .long 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da 283 .long 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7 284 .long 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967 285 .long 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13 286 .long 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85 287 .long 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3 288 .long 0xd192e819,0xd6990624,0xf40e3585,0x106aa070 289 .long 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5 290 .long 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3 291 .long 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208 292 .long 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2 293 ___ 294 } else { 295 $code.=<<___; 296 .align 64 297 .type $TABLE,\@object 298 $TABLE: 299 .quad 0x428a2f98d728ae22,0x7137449123ef65cd 300 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc 301 .quad 0x3956c25bf348b538,0x59f111f1b605d019 302 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118 303 .quad 0xd807aa98a3030242,0x12835b0145706fbe 304 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2 305 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1 306 .quad 0x9bdc06a725c71235,0xc19bf174cf692694 307 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3 308 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65 309 .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483 310 .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5 311 .quad 0x983e5152ee66dfab,0xa831c66d2db43210 312 .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4 313 .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725 314 .quad 0x06ca6351e003826f,0x142929670a0e6e70 315 .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926 316 .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df 317 .quad 0x650a73548baf63de,0x766a0abb3c77b2a8 318 .quad 0x81c2c92e47edaee6,0x92722c851482353b 319 .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001 320 .quad 0xc24b8b70d0f89791,0xc76c51a30654be30 321 .quad 0xd192e819d6ef5218,0xd69906245565a910 322 .quad 0xf40e35855771202a,0x106aa07032bbd1b8 323 .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53 324 .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8 325 .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb 326 .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3 327 .quad 0x748f82ee5defb2fc,0x78a5636f43172f60 328 .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec 329 .quad 0x90befffa23631e28,0xa4506cebde82bde9 330 .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b 331 .quad 0xca273eceea26619c,0xd186b8c721c0c207 332 .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178 333 .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6 334 .quad 0x113f9804bef90dae,0x1b710b35131c471b 335 .quad 0x28db77f523047d84,0x32caab7b40c72493 336 .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c 337 .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a 338 .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817 339 ___ 340 } 341 342 # EXCEPTION_DISPOSITION handler (EXCEPTION_RECORD *rec,ULONG64 frame, 343 # CONTEXT *context,DISPATCHER_CONTEXT *disp) 344 if ($win64) { 345 $rec="%rcx"; 346 $frame="%rdx"; 347 $context="%r8"; 348 $disp="%r9"; 349 350 $code.=<<___; 351 .extern __imp_RtlVirtualUnwind 352 .type se_handler,\@abi-omnipotent 353 .align 16 354 se_handler: 355 push %rsi 356 push %rdi 357 push %rbx 358 push %rbp 359 push %r12 360 push %r13 361 push %r14 362 push %r15 363 pushfq 364 sub \$64,%rsp 365 366 mov 120($context),%rax # pull context->Rax 367 mov 248($context),%rbx # pull context->Rip 368 369 lea .Lprologue(%rip),%r10 370 cmp %r10,%rbx # context->Rip<.Lprologue 371 jb .Lin_prologue 372 373 mov 152($context),%rax # pull context->Rsp 374 375 lea .Lepilogue(%rip),%r10 376 cmp %r10,%rbx # context->Rip>=.Lepilogue 377 jae .Lin_prologue 378 379 mov 16*$SZ+3*8(%rax),%rax # pull $_rsp 380 lea 48(%rax),%rax 381 382 mov -8(%rax),%rbx 383 mov -16(%rax),%rbp 384 mov -24(%rax),%r12 385 mov -32(%rax),%r13 386 mov -40(%rax),%r14 387 mov -48(%rax),%r15 388 mov %rbx,144($context) # restore context->Rbx 389 mov %rbp,160($context) # restore context->Rbp 390 mov %r12,216($context) # restore context->R12 391 mov %r13,224($context) # restore context->R13 392 mov %r14,232($context) # restore context->R14 393 mov %r15,240($context) # restore context->R15 394 395 .Lin_prologue: 396 mov 8(%rax),%rdi 397 mov 16(%rax),%rsi 398 mov %rax,152($context) # restore context->Rsp 399 mov %rsi,168($context) # restore context->Rsi 400 mov %rdi,176($context) # restore context->Rdi 401 402 mov 40($disp),%rdi # disp->ContextRecord 403 mov $context,%rsi # context 404 mov \$154,%ecx # sizeof(CONTEXT) 405 .long 0xa548f3fc # cld; rep movsq 406 407 mov $disp,%rsi 408 xor %rcx,%rcx # arg1, UNW_FLAG_NHANDLER 409 mov 8(%rsi),%rdx # arg2, disp->ImageBase 410 mov 0(%rsi),%r8 # arg3, disp->ControlPc 411 mov 16(%rsi),%r9 # arg4, disp->FunctionEntry 412 mov 40(%rsi),%r10 # disp->ContextRecord 413 lea 56(%rsi),%r11 # &disp->HandlerData 414 lea 24(%rsi),%r12 # &disp->EstablisherFrame 415 mov %r10,32(%rsp) # arg5 416 mov %r11,40(%rsp) # arg6 417 mov %r12,48(%rsp) # arg7 418 mov %rcx,56(%rsp) # arg8, (NULL) 419 call *__imp_RtlVirtualUnwind(%rip) 420 421 mov \$1,%eax # ExceptionContinueSearch 422 add \$64,%rsp 423 popfq 424 pop %r15 425 pop %r14 426 pop %r13 427 pop %r12 428 pop %rbp 429 pop %rbx 430 pop %rdi 431 pop %rsi 432 ret 433 .size se_handler,.-se_handler 434 435 .section .pdata 436 .align 4 437 .rva .LSEH_begin_$func 438 .rva .LSEH_end_$func 439 .rva .LSEH_info_$func 440 441 .section .xdata 442 .align 8 443 .LSEH_info_$func: 444 .byte 9,0,0,0 445 .rva se_handler 446 ___ 447 } 448 449 $code =~ s/\`([^\`]*)\`/eval $1/gem; 450 print $code; 451 close STDOUT; 452
