1 # IA-64 Itanium 2 possible unit masks 2 # 3 # The information for the following entries for the Itanium 2 4 # came from Intel Itanium 2 Processor Reference Manual For 5 # Software Development and Optimization, June 2002, Document 6 # number 251110-001. 7 8 name:zero type:mandatory default:0x0 9 0x0 No unit mask 10 11 # CPU_IA64_2 Table 11-37, 11-72 12 name:alat_capacity_miss type:bitmask default:0x03 13 0x1 INT 14 0x2 FP 15 0x3 ALL 16 17 # CPU_IA64_2 Table 11-38 18 name:back_end_bubble type:exclusive default:0x00 19 0x0 ALL 20 0x1 FE 21 0x2 L1D_FPU_RSE 22 23 # CPU_IA64_2 Table 11-39 24 name:be_br_mispredict_detail type:exclusive default:0x00 25 0x0 ANY 26 0x1 STG 27 0x2 ROT 28 0x3 PFS 29 30 # CPU_IA64_2 Table 11-40 31 name:be_exe_bubble type:exclusive default:0x00 32 0x0 ALL 33 0x1 GRALL 34 0x2 FRALL 35 0x3 PR 36 0x4 ARCR 37 0x5 GRCR 38 0x6 CANCEL 39 0x7 BANK_SWITCH 40 0x8 ARCR_PR_CANCEL_BANK 41 42 # CPU_IA64_2 Table 11-41 43 name:be_flush_bubble type:exclusive default:0x00 44 0x0 ALL 45 0x1 BRU 46 0x2 XPN 47 48 # CPU_IA64_2 Table 11-42 49 name:be_l1d_fpu_bubble type:exclusive default:0x00 50 0x0 ALL 51 0x1 FPU 52 0x2 L1D 53 0x3 L1D_FULLSTBUF 54 0x4 L1D_DCURECIR 55 0x5 L1D_HPW 56 0x7 L1D_FILLCONF 57 0x8 L1D_DCS 58 0x9 L1D_L2BPRESS 59 0xa L1D_TLB 60 0xb L1D_LDCONF 61 0xc L1D_LDCHK 62 0xd L1D_NAT 63 0xe L1D_STBUFRECIR 64 0xf L1D_NATCONF 65 66 # CPU_IA64_2 Table 11-43 67 # FIXME: events using this is commented out in events 68 #name:be_lost_bw_due_to_fe type:exclusive default:0x00 69 # 0x0 ALL 70 # 0x1 FEFLUSH 71 # 0x4 UNREACHED 72 # 0x5 IBFULL 73 # 0x6 IMISS 74 # 0x7 TLBMISS 75 # 0x8 FILL_RECIRC 76 # 0x9 BI 77 # 0xa BRQ 78 # 0xb PLP 79 # 0xc BR_ILOCK 80 # 0xd BUBBLE 81 82 # CPU_IA64_2 Table 11-44 83 name:be_rse_bubble type:exclusive default:0x00 84 0x0 ALL 85 0x1 BANK_SWITCH 86 0x2 AR_DEP 87 0x3 OVERFLOW 88 0x4 UNDERFLOW 89 0x5 LOADRS 90 91 # CPU_IA64_2 Table 11-45 92 name:br_mispred_detail type:exclusive default:0x00 93 0x0 ALL.ALL_PRED 94 0x1 ALL.CORRECT_PRED 95 0x2 ALL.WRONG_PATH 96 0x3 ALL.WRONG_TARGET 97 0x4 IPREL.ALL_PRED 98 0x5 IPREL.CORRECT_PRED 99 0x6 IPREL.WRONG_PATH 100 0x7 IPREL.WRONG_TARGET 101 0x8 RETURN.ALL_PRED 102 0x9 RETURN.CORRECT_PRED 103 0xa RETURN.WRONG_PATH 104 0xb RETURN.WRONG_TARGET 105 0xc NRETIND.ALL_PRED 106 0xd NRETIND.CORRECT_PRED 107 0xe NRETIND.WRONG_PATH 108 0xf NRETIND.WRONG_TARGET 109 110 # CPU_IA64_2 Table 11-46 111 name:br_mispredict_detail2 type:exclusive default:0x00 112 0x0 ALL.ALL_UNKNOWN_PRED 113 0x1 ALL.UKNOWN_PATH_CORRECT_PRED 114 0x2 ALL.UKNOWN_PATH_WRONG_PATH 115 0x4 IPREL.ALL_UNKNOWN_PRED 116 0x5 IPREL.UNKNOWN_PATH_CORRECT_PRED 117 0x6 IPREL.UNKNOWN_PATH_WRONG_PATH 118 0x8 RETURN.ALL_UNKNOWN_PRED 119 0x9 RETURN.UNKNOWN_PATH_CORRECT_PRED 120 0xa RETURN.UNKNOWN_PATH_WRONG_PATH 121 0xc NRETIND.ALL_UNKNOWN_PRED 122 0xd NRETIND.UNKNOWN_PATH_CORRECT_PRED 123 0xe NRETIND.UNKNOWN_PATH_WRONG_PATH 124 125 # CPU_IA64_2 Table 11-47 126 name:br_path_pred type:exclusive default:0x00 127 0x0 ALL.MISPRED_NOTTAKEN 128 0x1 ALL.MISPRED_TAKEN 129 0x2 ALL.OKPRED_NOTTAKEN 130 0x3 ALL.OKPRED_TAKEN 131 0x4 IPREL.MISPRED_NOTTAKEN 132 0x5 IPREL.MISPRED_TAKEN 133 0x6 IPREL.OKPRED_NOTTAKEN 134 0x7 IPREL.OKPRED_TAKEN 135 0x8 RETURN.MISPRED_NOTTAKEN 136 0x9 RETURN.MISPRED_TAKEN 137 0xa RETURN.OKPRED_NOTTAKEN 138 0xb RETURN.OKPRED_TAKEN 139 0xc NRETIND.MISPRED_NOTTAKEN 140 0xd NRETIND.MISPRED_TAKEN 141 0xe NRETIND.OKPRED_NOTTAKEN 142 0xf NRETIND.OKPRED_TAKEN 143 144 # CPU_IA64_2 Table 11-48 145 name:br_path_pred2 type:exclusive default:0x00 146 0x0 ALL.UNKNOWNPRED_NOTTAKEN 147 0x1 ALL.UNKNOWNPRED_TAKEN 148 0x4 IPREL.UNKNOWNPRED_NOTTAKEN 149 0x5 IPREL.UNKNOWNPRED__TAKEN 150 0x8 RETURN.UNKNOWNPRED_NOTTAKEN 151 0x9 RETURN.UNKNOWNPRED_TAKEN 152 0xc NRETIND.UNKNOWNPRED_NOTTAKEN 153 0xd NRETIND.UNKNOWNPRED_TAKEN 154 155 # CPU_IA64_2 Table 11-49, 11-51, 11-55, 11-56, 11-57, 11-58 156 name:bus type:exclusive default:0x03 157 0x1 IO 158 0x2 SELF 159 0x3 ANY 160 161 # CPU_IA64_2 Table 11-50 b0001 162 name:bus_backsnp_req type:mandatory default:0x01 163 0x1 0x0 164 165 # CPU_IA64_2 Table 11-52 166 name:bus_lock type:exclusive default:0x03 167 0x2 SELF 168 0x3 ANY 169 170 # CPU_IA64_2 Table 11-53 171 name:bus_memory type:exclusive default:0x0f 172 0x5 EQ_128BYTEIO 173 0x6 EQ_128BYTE_SELF 174 0x7 EQ_128BYTE_ANY 175 0x9 LT_128BYTEIO 176 0xa LT_128BYTE_SELF 177 0xb LT_128BYTE_ANY 178 0xd ALL IO 179 0xe ALL SELF 180 0xf ALL ANY 181 182 # CPU_IA64_2 Table 11-54 183 name:bus_mem_read type:exclusive default:0x0f 184 0x1 BIL IO 185 0x2 BIL SELF 186 0x3 BIL ANY 187 0x5 BRL IO 188 0x6 BRL SELF 189 0x7 BRL_ANY 190 0x9 BRIL IO 191 0xa BRIL SELF 192 0xb BRIL ANY 193 0xd ALL IO 194 0xe ALL SELF 195 0xf ALL ANY 196 197 # CPU_IA64_2 Table 11-59, 11-60 198 name:bus_snoop type:exclusive default:0x03 199 0x2 SELF 200 0x3 ANY 201 202 # CPU_IA64_2 Table 11-61 203 name:bus_wr_wb type:exclusive default:0x0f 204 0x5 EQ_128BYTE IO 205 0x6 EQ_128BYTE SELF 206 0x7 EQ_128BYTE ANY 207 0xa CCASTOUT SELF 208 0xb CCASTOUT ANY 209 0xd ALL IO 210 0xe ALL SELF 211 0xf ALL ANY 212 213 # CPU_IA64_2 Table 11-62 214 name:encbr_mispred_detail type:exclusive default:0x0 215 0x0 ALL.ALL_PRED 216 0x1 ALL.CORRECT_PRED 217 0x2 ALL.WRONG_PATH 218 0x3 ALL.WRONG_TARGET 219 0x8 OVERSUB.ALL_PRED 220 0x9 OVERSUB.CORRECT_PRED 221 0xa OVERSUB.CORRECT_PRED 222 0xb OVERSUB.WRONGPATH 223 0xc ALL2.ALL_PRED 224 0xd ALL2.CORRECT_PRED 225 0xe ALL2.WRONG_PATH 226 0xf ALL2.WRONG_TARGET 227 228 # CPU_IA64_2 Table 11-63 229 name:extern_dp_pins_0_to_3 type:bitmask default:0xf 230 0x1 PIN0 231 0x2 PIN1 232 0x4 PIN2 233 0x8 PIN3 234 0xf ALL 235 236 # CPU_IA64_2 Table 11-64 237 name:extern_dp_pins_4_to_5 type:bitmask default:0x03 238 0x1 PIN4 239 0x2 PIN5 240 0xf ALL 241 242 # CPU_IA64_2 Table 11-65 243 name:fe_bubble type:exclusive default:0x0 244 0x0 ALL 245 0x1 FEFLUSH 246 0x3 GROUP1 247 0x4 GROUP2 248 0x5 IBFULL 249 0x6 IMISS 250 0x7 TLBMISS 251 0x8 FILL_RECIRC 252 0x9 BRANCH 253 0xa GROUP3 254 0xb ALLBUT_FEFLUSH_BUBBLE 255 0xc ALLBUT_IBFULL 256 0xd BUBBLE 257 258 # CPU_IA64_2 Table 11-66, 11-69*/ 259 name:fe_lost type:exclusive default:0x0 260 0x0 ALL 261 0x1 FEFLUSH 262 0x4 UNREACHED 263 0x5 IBFULL 264 0x6 IMISS 265 0x7 TLBMISS 266 0x8 FILL_RECIRC 267 0x9 BI 268 0xa BRQ 269 0xb PLP 270 0xc BR_ILOCK 271 0xd BUBBLE 272 273 # CPU_IA64_2 Table 11-67, 11-79, 11-86, 11-90, 11-92 b0000 274 # FIXME: events using this is commented out in events 275 #name:this type:exclusive default:0x0 276 # 0x0 THIS 277 278 # CPU_IA64_2 Table 11-68 279 name:tagged_inst_retired type:exclusive default:0x0 280 0x0 IBRP0_PMB8 281 0x1 IBRP1_PMB9 282 0x2 IBRP2_PMC8 283 0x3 IBRP3_PMC9 284 285 # CPU_IA64_2 Table 11-73 286 name:itlb_misses_fetch type:exclusive default:0x3 287 0x1 L1ITLB 288 0x2 L2ITLB 289 0x3 ALL 290 291 # CPU_IA64_2 Table 11-74 292 name:l1d_read_misses type:exclusive default:0x0 293 0x0 ALL 294 0x1 RSE_FILL 295 296 # CPU_IA64_2 Table 11-75 297 name:l1i_prefetch_stall type:exclusive default:0x3 298 0x2 FLOW 299 0x3 ALL 300 301 # CPU_IA64_2 Table 11-76, 11-91 b0000 302 # FIXME: events using this is commented out in events 303 #name:l2_lines type:exclusive default:0x0 304 # 0x0 ANY 305 306 # CPU_IA64_2 Table 11-77 307 name:l2_bypass type:exclusive default:0x0 308 0x0 L2_DATA1 309 0x1 L2_DATA2 310 0x2 L3_DATA1 311 0x4 L2_INST1 312 0x5 L2_INST2 313 0x6 L3_INST1 314 315 # CPU_IA64_2 Table 11-78 316 # FIXME: events using this is commented out in events 317 #name:l2_data_references type:bitmask default:0x3 318 # 0x1 L2_DATA_READS 319 # 0x2 L2_DATA_WRITES 320 # 0x3 L2_ALL 321 322 # CPU_IA64_2 Table 11-80 323 name:l2_force_recirc type:exclusive default:0x0 324 0x0 ANY 325 0x1 SMC_HIT 326 0x2 L1W 327 0x4 TAG_NOTOK 328 0x5 TRAN_PREF 329 0x6 SNP_OR_L3 330 0x8 VIC_PEND 331 0x9 FILL_HIT 332 0xa IPF_MISS 333 0xb VIC_BUF_FULL 334 0xc OZQ_MISS 335 0xd SAME_INDEX 336 0xe FRC_RECIRC 337 338 # CPU_IA64_2 Table 11-81, 11-83 b1000 339 name:recirc_ifetch type:mandatory default:0x8 340 0x8 default:0x0} } }; 341 342 # CPU_IA64_2 Table 11-82 343 name:l2_ifet_cancels type:exclusive default:0x0 344 0x0 ANY 345 0x2 BYPASS 346 0x4 DIDNT_RECIR 347 0x5 RECIRC_OVER_SUB 348 0x6 ST_FILL_WB 349 0x7 DATA_RD 350 0x8 PREEMPT 351 0xc CHG_PRIO 352 0xd IFETCH_BYP 353 354 # CPU_IA64_2 Table 11-84 355 name:l2_l3_access_cancel type:exclusive default:0x9 356 0x1 SPEC_L3_BYP 357 0x2 FILLD_FULL 358 0x5 UC_BLOCKED 359 0x6 INV_L3_BYP 360 0x8 EBL_REJECT 361 0x9 ANY 362 0xa DFETCH 363 0xb IFETCH 364 365 # CPU_IA64_2 Table 11-85 366 name:l2_ops_issued type:exclusive default:0x8 367 0x8 INT_LOAD 368 0x9 FP_LOAD 369 0xa RMW 370 0xb STORE 371 0xc NST_NLD 372 373 # CPU_IA64_2 Table 11-87 374 name:l2_ozq_cancels0 type:exclusive default:0x0 375 0x0 ANY 376 0x1 LATE_SPEC_BYP 377 0x2 LATE_RELEASE 378 0x3 LATE_ACQUIRE 379 0x4 LATE_BYP_EFFRELEASE 380 381 # CPU_IA64_2 Table 11-88 382 name:l2_ozq_cancels1 type:exclusive default:0x1 383 0x0 REL 384 0x1 BANK_CONF 385 0x2 L2D_ST_MAT 386 0x4 SYNC 387 0x5 HPW_IFETCH_CONF 388 0x6 CANC_L2M_ST 389 0x7 L1_FILL_CONF 390 0x8 ST_FILL_CONF 391 0x9 CCV 392 0xa SEM 393 0xb L2M_ST_MAT 394 0xc MFA 395 0xd L2A_ST_MAT 396 0xe L1DF_L2M 397 0xf ECC 398 399 # CPU_IA64_2 Table 11-89 400 name:l2_ozq_cancels2 type:exclusive default:0x0 401 0x0 RECIRC_OVER_SUB 402 0x1 CANC_L2C_ST 403 0x2 L2C_ST_MAT 404 0x3 SCRUB 405 0x4 ACQ 406 0x5 READ_WB_CONF 407 0x6 OZ_DATA_CONF 408 0x8 L2FILL_ST_CONF 409 0x9 DIDNT_RECIRC 410 0xa WEIRD 411 0xc OVER_SUB 412 0xd CANC_L2D_ST 413 0xf D_IFET 414 415 # CPU_IA64_2 Table 11-93 416 name:l3_reads type:exclusive default:0x3 417 0x1 DINST_FETCH.HIT 418 0x2 DINST_FETCH.MISS 419 0x3 DINST_FETCH.ALL 420 0x5 INST_FETCH.HIT 421 0x6 INST_FETCH.MISS 422 0x7 INST_FETCH.ALL 423 0x9 DATA_READ.HIT 424 0xa DATA_READ.MISS 425 0xb DATA_READ.ALL 426 0xd ALL.HIT 427 0xe ALL.MISS 428 0xf ALL.ALL 429 430 # CPU_IA64_2 Table 11-94 431 name:l3_writes type:exclusive default:0x7 432 0x5 DATA_WRITE.HIT 433 0x6 DATA_WRITE.MISS 434 0x7 DATA_WRITE.ALL 435 0x9 L2_WB.HIT 436 0xa L2_WB.MISS 437 0xb L2_WB.ALL 438 0xd ALL.HIT 439 0xe ALL.MISS 440 0xf ALL.ALL 441 442 # CPU_IA64_2 Table 11-95 443 name:mem_read_current type:exclusive default:0x3 444 0x1 IO 445 0x3 ANY 446 447 # CPU_IA64_2 Table 11-96 448 name:rse_references_retired type:bitmask default:0x3 449 0x1 LOAD 450 0x2 STORE 451 0x3 ALL 452 453 # CPU_IA64_2 Table 11-97 bitmask 454 name:syll_not_dispersed type:bitmask default:0xf 455 0x1 EXPL 456 0x2 IMPL 457 0x4 FE 458 0x8 MLI 459 0xf ALL 460 461 # CPU_IA64_2 Table 11-98 462 name:syll_overcount type:exclusive default:0x3 463 0x1 EXPL 464 0x2 IMPL 465 0x3 ALL 466
