1 @/* 2 @ ** Copyright 2003-2010, VisualOn, Inc. 3 @ ** 4 @ ** Licensed under the Apache License, Version 2.0 (the "License"); 5 @ ** you may not use this file except in compliance with the License. 6 @ ** You may obtain a copy of the License at 7 @ ** 8 @ ** http://www.apache.org/licenses/LICENSE-2.0 9 @ ** 10 @ ** Unless required by applicable law or agreed to in writing, software 11 @ ** distributed under the License is distributed on an "AS IS" BASIS, 12 @ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 @ ** See the License for the specific language governing permissions and 14 @ ** limitations under the License. 15 @ */ 16 @ 17 @void Syn_filt_32( 18 @ Word16 a[], /* (i) Q12 : a[m+1] prediction coefficients */ 19 @ Word16 m, /* (i) : order of LP filter */ 20 @ Word16 exc[], /* (i) Qnew: excitation (exc[i] >> Qnew) */ 21 @ Word16 Qnew, /* (i) : exc scaling = 0(min) to 8(max) */ 22 @ Word16 sig_hi[], /* (o) /16 : synthesis high */ 23 @ Word16 sig_lo[], /* (o) /16 : synthesis low */ 24 @ Word16 lg /* (i) : size of filtering */ 25 @) 26 @*************************************************************** 27 @ 28 @ a[] --- r0 29 @ m --- r1 30 @ exc[] --- r2 31 @ Qnew --- r3 32 @ sig_hi[] --- r4 33 @ sig_lo[] --- r5 34 @ lg --- r6 35 36 .section .text 37 .global Syn_filt_32_asm 38 39 Syn_filt_32_asm: 40 41 STMFD r13!, {r4 - r12, r14} 42 LDR r4, [r13, #40] @ get sig_hi[] address 43 LDR r5, [r13, #44] @ get sig_lo[] address 44 45 LDRSH r6, [r0] @ load Aq[0] 46 ADD r7, r3, #4 @ 4 + Q_new 47 MOV r3, r6, ASR r7 @ a0 = Aq[0] >> (4 + Q_new) 48 49 LDR r14, =0xffff 50 LDRSH r6, [r0, #2] @ load Aq[1] 51 LDRSH r7, [r0, #4] @ load Aq[2] 52 LDRSH r8, [r0, #6] @ load Aq[3] 53 LDRSH r9, [r0, #8] @ load Aq[4] 54 AND r6, r6, r14 55 AND r8, r8, r14 56 ORR r10, r6, r7, LSL #16 @ Aq[2] -- Aq[1] 57 ORR r11, r8, r9, LSL #16 @ Aq[4] -- Aq[3] 58 STR r10, [r13, #-4] 59 STR r11, [r13, #-8] 60 61 LDRSH r6, [r0, #10] @ load Aq[5] 62 LDRSH r7, [r0, #12] @ load Aq[6] 63 LDRSH r8, [r0, #14] @ load Aq[7] 64 LDRSH r9, [r0, #16] @ load Aq[8] 65 AND r6, r6, r14 66 AND r8, r8, r14 67 ORR r10, r6, r7, LSL #16 @ Aq[6] -- Aq[5] 68 ORR r11, r8, r9, LSL #16 @ Aq[8] -- Aq[7] 69 STR r10, [r13, #-12] 70 STR r11, [r13, #-16] 71 72 LDRSH r6, [r0, #18] @ load Aq[9] 73 LDRSH r7, [r0, #20] @ load Aq[10] 74 LDRSH r8, [r0, #22] @ load Aq[11] 75 LDRSH r9, [r0, #24] @ load Aq[12] 76 AND r6, r6, r14 77 AND r8, r8, r14 78 ORR r10, r6, r7, LSL #16 @ Aq[10] -- Aq[9] 79 ORR r11, r8, r9, LSL #16 @ Aq[12] -- Aq[11] 80 STR r10, [r13, #-20] 81 STR r11, [r13, #-24] 82 83 LDRSH r6, [r0, #26] @ load Aq[13] 84 LDRSH r7, [r0, #28] @ load Aq[14] 85 LDRSH r8, [r0, #30] @ load Aq[15] 86 LDRSH r9, [r0, #32] @ load Aq[16] 87 AND r6, r6, r14 88 AND r8, r8, r14 89 ORR r10, r6, r7, LSL #16 @ Aq[14] -- Aq[13] 90 ORR r11, r8, r9, LSL #16 @ Aq[16] -- Aq[15] 91 STR r10, [r13, #-28] 92 STR r11, [r13, #-32] 93 94 MOV r8, #0 @ i = 0 95 96 LOOP: 97 LDRSH r6, [r5, #-2] @ load sig_lo[i-1] 98 LDRSH r7, [r5, #-4] @ load sig_lo[i-2] 99 100 LDR r11, [r13, #-4] @ Aq[2] -- Aq[1] 101 LDRSH r9, [r5, #-6] @ load sig_lo[i-3] 102 LDRSH r10, [r5, #-8] @ load sig_lo[i-4] 103 104 SMULBB r12, r6, r11 @ sig_lo[i-1] * Aq[1] 105 106 LDRSH r6, [r5, #-10] @ load sig_lo[i-5] 107 SMLABT r12, r7, r11, r12 @ sig_lo[i-2] * Aq[2] 108 LDR r11, [r13, #-8] @ Aq[4] -- Aq[3] 109 LDRSH r7, [r5, #-12] @ load sig_lo[i-6] 110 SMLABB r12, r9, r11, r12 @ sig_lo[i-3] * Aq[3] 111 LDRSH r9, [r5, #-14] @ load sig_lo[i-7] 112 SMLABT r12, r10, r11, r12 @ sig_lo[i-4] * Aq[4] 113 LDR r11, [r13, #-12] @ Aq[6] -- Aq[5] 114 LDRSH r10, [r5, #-16] @ load sig_lo[i-8] 115 SMLABB r12, r6, r11, r12 @ sig_lo[i-5] * Aq[5] 116 LDRSH r6, [r5, #-18] @ load sig_lo[i-9] 117 SMLABT r12, r7, r11, r12 @ sig_lo[i-6] * Aq[6] 118 LDR r11, [r13, #-16] @ Aq[8] -- Aq[7] 119 LDRSH r7, [r5, #-20] @ load sig_lo[i-10] 120 SMLABB r12, r9, r11, r12 @ sig_lo[i-7] * Aq[7] 121 LDRSH r9, [r5, #-22] @ load sig_lo[i-11] 122 SMLABT r12, r10, r11, r12 @ sig_lo[i-8] * Aq[8] 123 LDR r11, [r13, #-20] @ Aq[10] -- Aq[9] 124 LDRSH r10,[r5, #-24] @ load sig_lo[i-12] 125 SMLABB r12, r6, r11, r12 @ sig_lo[i-9] * Aq[9] 126 LDRSH r6, [r5, #-26] @ load sig_lo[i-13] 127 SMLABT r12, r7, r11, r12 @ sig_lo[i-10] * Aq[10] 128 LDR r11, [r13, #-24] @ Aq[12] -- Aq[11] 129 LDRSH r7, [r5, #-28] @ load sig_lo[i-14] 130 SMLABB r12, r9, r11, r12 @ sig_lo[i-11] * Aq[11] 131 LDRSH r9, [r5, #-30] @ load sig_lo[i-15] 132 SMLABT r12, r10, r11, r12 @ sig_lo[i-12] * Aq[12] 133 134 LDR r11, [r13, #-28] @ Aq[14] -- Aq[13] 135 LDRSH r10, [r5, #-32] @ load sig_lo[i-16] 136 SMLABB r12, r6, r11, r12 @ sig_lo[i-13] * Aq[13] 137 SMLABT r12, r7, r11, r12 @ sig_lo[i-14] * Aq[14] 138 139 LDR r11, [r13, #-32] @ Aq[16] -- Aq[15] 140 LDRSH r6, [r2],#2 @ load exc[i] 141 SMLABB r12, r9, r11, r12 @ sig_lo[i-15] * Aq[15] 142 SMLABT r12, r10, r11, r12 @ sig_lo[i-16] * Aq[16] 143 MUL r7, r6, r3 @ exc[i] * a0 144 RSB r14, r12, #0 @ L_tmp 145 MOV r14, r14, ASR #11 @ L_tmp >>= 11 146 ADD r14, r14, r7, LSL #1 @ L_tmp += (exc[i] * a0) << 1 147 148 149 LDRSH r6, [r4, #-2] @ load sig_hi[i-1] 150 LDRSH r7, [r4, #-4] @ load sig_hi[i-2] 151 152 LDR r11, [r13, #-4] @ Aq[2] -- Aq[1] 153 LDRSH r9, [r4, #-6] @ load sig_hi[i-3] 154 LDRSH r10, [r4, #-8] @ load sig_hi[i-4] 155 SMULBB r12, r6, r11 @ sig_hi[i-1] * Aq[1] 156 LDRSH r6, [r4, #-10] @ load sig_hi[i-5] 157 SMLABT r12, r7, r11, r12 @ sig_hi[i-2] * Aq[2] 158 159 LDR r11, [r13, #-8] @ Aq[4] -- Aq[3] 160 LDRSH r7, [r4, #-12] @ load sig_hi[i-6] 161 162 SMLABB r12, r9, r11, r12 @ sig_hi[i-3] * Aq[3] 163 LDRSH r9, [r4, #-14] @ load sig_hi[i-7] 164 165 SMLABT r12, r10, r11, r12 @ sig_hi[i-4] * Aq[4] 166 167 LDR r11, [r13, #-12] @ Aq[6] -- Aq[5] 168 LDRSH r10, [r4, #-16] @ load sig_hi[i-8] 169 170 SMLABB r12, r6, r11, r12 @ sig_hi[i-5] * Aq[5] 171 172 LDRSH r6, [r4, #-18] @ load sig_hi[i-9] 173 SMLABT r12, r7, r11, r12 @ sig_hi[i-6] * Aq[6] 174 175 LDR r11, [r13, #-16] @ Aq[8] -- Aq[7] 176 LDRSH r7, [r4, #-20] @ load sig_hi[i-10] 177 178 SMLABB r12, r9, r11, r12 @ sig_hi[i-7] * Aq[7] 179 180 LDRSH r9, [r4, #-22] @ load sig_hi[i-11] 181 182 SMLABT r12, r10, r11, r12 @ sig_hi[i-8] * Aq[8] 183 184 LDR r11, [r13, #-20] @ Aq[10] -- Aq[9] 185 LDRSH r10,[r4, #-24] @ load sig_hi[i-12] 186 187 SMLABB r12, r6, r11, r12 @ sig_hi[i-9] * Aq[9] 188 LDRSH r6, [r4, #-26] @ load sig_hi[i-13] 189 SMLABT r12, r7, r11, r12 @ sig_hi[i-10] * Aq[10] 190 191 LDR r11, [r13, #-24] @ Aq[12] -- Aq[11] 192 LDRSH r7, [r4, #-28] @ load sig_hi[i-14] 193 SMLABB r12, r9, r11, r12 @ sig_hi[i-11] * Aq[11] 194 LDRSH r9, [r4, #-30] @ load sig_hi[i-15] 195 SMLABT r12, r10, r11, r12 @ sig_hi[i-12] * Aq[12] 196 197 LDR r11, [r13, #-28] @ Aq[14] -- Aq[13] 198 LDRSH r10, [r4, #-32] @ load sig_hi[i-16] 199 SMLABB r12, r6, r11, r12 @ sig_hi[i-13] * Aq[13] 200 SMLABT r12, r7, r11, r12 @ sig_hi[i-14] * Aq[14] 201 202 LDR r11, [r13, #-32] @ Aq[16] -- Aq[15] 203 SMLABB r12, r9, r11, r12 @ sig_hi[i-15] * Aq[15] 204 SMLABT r12, r10, r11, r12 @ sig_hi[i-16] * Aq[16] 205 ADD r6, r12, r12 @ r12 << 1 206 SUB r14, r14, r6 207 MOV r14, r14, LSL #3 @ L_tmp <<=3 208 209 MOV r7, r14, ASR #16 @ L_tmp >> 16 210 211 MOV r14, r14, ASR #4 @ L_tmp >>=4 212 STRH r7, [r4], #2 @ sig_hi[i] = L_tmp >> 16 213 SUB r9, r14, r7, LSL #12 @ sig_lo[i] = L_tmp - (sig_hi[i] << 12) 214 215 ADD r8, r8, #1 216 STRH r9, [r5], #2 217 CMP r8, #64 218 BLT LOOP 219 220 Syn_filt_32_end: 221 222 LDMFD r13!, {r4 - r12, r15} 223 @ENDFUNC 224 .END 225 226 227
