Lines Matching full:cycles
77 // 33 cycles (multiply also calculates its result in IWB). For all
82 // The L1 cache hit latency is four cycles for floating point loads
83 // and three cycles for integer loads.
96 // have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that
97 // update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
98 // loads take 4 cycles (for L1 hit).
