1 //===-- PPCSchedule440.td - PPC 440 Scheduling Definitions -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 // Primary reference: 11 // PowerPC 440x6 Embedded Processor Core User's Manual. 12 // IBM (as updated in) 2010. 13 14 // The basic PPC 440 does not include a floating-point unit; the pipeline 15 // timings here are constructed to match the FP2 unit shipped with the 16 // PPC-440- and PPC-450-based Blue Gene (L and P) supercomputers. 17 // References: 18 // S. Chatterjee, et al. Design and exploitation of a high-performance 19 // SIMD floating-point unit for Blue Gene/L. 20 // IBM J. Res. & Dev. 49 (2/3) March/May 2005. 21 // also: 22 // Carlos Sosa and Brant Knudson. IBM System Blue Gene Solution: 23 // Blue Gene/P Application Development. 24 // IBM (as updated in) 2009. 25 26 //===----------------------------------------------------------------------===// 27 // Functional units on the PowerPC 440/450 chip sets 28 // 29 def IFTH1 : FuncUnit; // Fetch unit 1 30 def IFTH2 : FuncUnit; // Fetch unit 2 31 def PDCD1 : FuncUnit; // Decode unit 1 32 def PDCD2 : FuncUnit; // Decode unit 2 33 def DISS1 : FuncUnit; // Issue unit 1 34 def DISS2 : FuncUnit; // Issue unit 2 35 def LRACC : FuncUnit; // Register access and dispatch for 36 // the simple integer (J-pipe) and 37 // load/store (L-pipe) pipelines 38 def IRACC : FuncUnit; // Register access and dispatch for 39 // the complex integer (I-pipe) pipeline 40 def FRACC : FuncUnit; // Register access and dispatch for 41 // the floating-point execution (F-pipe) pipeline 42 def IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline 43 def IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline 44 def IWB : FuncUnit; // Write-back unit for the I pipeline 45 def JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline 46 def JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline 47 def JWB : FuncUnit; // Write-back unit for the J pipeline 48 def AGEN : FuncUnit; // Address generation for the L pipeline 49 def CRD : FuncUnit; // D-cache access for the L pipeline 50 def LWB : FuncUnit; // Write-back unit for the L pipeline 51 def FEXE1 : FuncUnit; // Execution stage 1 for the F pipeline 52 def FEXE2 : FuncUnit; // Execution stage 2 for the F pipeline 53 def FEXE3 : FuncUnit; // Execution stage 3 for the F pipeline 54 def FEXE4 : FuncUnit; // Execution stage 4 for the F pipeline 55 def FEXE5 : FuncUnit; // Execution stage 5 for the F pipeline 56 def FEXE6 : FuncUnit; // Execution stage 6 for the F pipeline 57 def FWB : FuncUnit; // Write-back unit for the F pipeline 58 59 def LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used 60 // to make sure that no lwarx/stwcx. 61 // instructions are issued while another 62 // lwarx/stwcx. is in the L pipe. 63 64 def GPR_Bypass : Bypass; // The bypass for general-purpose regs. 65 def FPR_Bypass : Bypass; // The bypass for floating-point regs. 66 67 // Notes: 68 // Instructions are held in the FRACC, LRACC and IRACC pipeline 69 // stages until their source operands become ready. Exceptions: 70 // - Store instructions will hold in the AGEN stage 71 // - The integer multiply-accumulate instruction will hold in 72 // the IEXE1 stage 73 // 74 // For most I-pipe operations, the result is available at the end of 75 // the IEXE1 stage. Operations such as multiply and divide must 76 // continue to execute in IEXE2 and IWB. Divide resides in IWB for 77 // 33 cycles (multiply also calculates its result in IWB). For all 78 // J-pipe instructions, the result is available 79 // at the end of the JEXE1 stage. Loads have a 3-cycle latency 80 // (data is not available until after the LWB stage). 81 // 82 // The L1 cache hit latency is four cycles for floating point loads 83 // and three cycles for integer loads. 84 // 85 // The stwcx. instruction requires both the LRACC and the IRACC 86 // dispatch stages. It must be issued from DISS0. 87 // 88 // All lwarx/stwcx. instructions hold in LRACC if another 89 // uncommitted lwarx/stwcx. is in AGEN, CRD, or LWB. 90 // 91 // msync (a.k.a. sync) and mbar will hold in LWB until all load/store 92 // resources are empty. AGEN and CRD are held empty until the msync/mbar 93 // commits. 94 // 95 // Most floating-point instructions, computational and move, 96 // have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that 97 // update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above, 98 // loads take 4 cycles (for L1 hit). 99 100 // 101 // This file defines the itinerary class data for the PPC 440 processor. 102 // 103 //===----------------------------------------------------------------------===// 104 105 106 def PPC440Itineraries : ProcessorItineraries< 107 [IFTH1, IFTH2, PDCD1, PDCD2, DISS1, DISS2, FRACC, 108 IRACC, IEXE1, IEXE2, IWB, LRACC, JEXE1, JEXE2, JWB, AGEN, CRD, LWB, 109 FEXE1, FEXE2, FEXE3, FEXE4, FEXE5, FEXE6, FWB, LWARX_Hold], 110 [GPR_Bypass, FPR_Bypass], [ 111 InstrItinData<IntSimple , [InstrStage<1, [IFTH1, IFTH2]>, 112 InstrStage<1, [PDCD1, PDCD2]>, 113 InstrStage<1, [DISS1, DISS2]>, 114 InstrStage<1, [IRACC, LRACC]>, 115 InstrStage<1, [IEXE1, JEXE1]>, 116 InstrStage<1, [IEXE2, JEXE2]>, 117 InstrStage<1, [IWB, JWB]>], 118 [6, 4, 4], 119 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 120 InstrItinData<IntGeneral , [InstrStage<1, [IFTH1, IFTH2]>, 121 InstrStage<1, [PDCD1, PDCD2]>, 122 InstrStage<1, [DISS1, DISS2]>, 123 InstrStage<1, [IRACC, LRACC]>, 124 InstrStage<1, [IEXE1, JEXE1]>, 125 InstrStage<1, [IEXE2, JEXE2]>, 126 InstrStage<1, [IWB, JWB]>], 127 [6, 4, 4], 128 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 129 InstrItinData<IntCompare , [InstrStage<1, [IFTH1, IFTH2]>, 130 InstrStage<1, [PDCD1, PDCD2]>, 131 InstrStage<1, [DISS1, DISS2]>, 132 InstrStage<1, [IRACC, LRACC]>, 133 InstrStage<1, [IEXE1, JEXE1]>, 134 InstrStage<1, [IEXE2, JEXE2]>, 135 InstrStage<1, [IWB, JWB]>], 136 [6, 4, 4], 137 [NoBypass, GPR_Bypass, GPR_Bypass]>, 138 InstrItinData<IntDivW , [InstrStage<1, [IFTH1, IFTH2]>, 139 InstrStage<1, [PDCD1, PDCD2]>, 140 InstrStage<1, [DISS1, DISS2]>, 141 InstrStage<1, [IRACC]>, 142 InstrStage<1, [IEXE1]>, 143 InstrStage<1, [IEXE2]>, 144 InstrStage<33, [IWB]>], 145 [40, 4, 4], 146 [NoBypass, GPR_Bypass, GPR_Bypass]>, 147 InstrItinData<IntMFFS , [InstrStage<1, [IFTH1, IFTH2]>, 148 InstrStage<1, [PDCD1, PDCD2]>, 149 InstrStage<1, [DISS1, DISS2]>, 150 InstrStage<1, [IRACC]>, 151 InstrStage<1, [IEXE1]>, 152 InstrStage<1, [IEXE2]>, 153 InstrStage<1, [IWB]>], 154 [7, 4, 4], 155 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 156 InstrItinData<IntMTFSB0 , [InstrStage<1, [IFTH1, IFTH2]>, 157 InstrStage<1, [PDCD1, PDCD2]>, 158 InstrStage<1, [DISS1, DISS2]>, 159 InstrStage<1, [IRACC]>, 160 InstrStage<1, [IEXE1]>, 161 InstrStage<1, [IEXE2]>, 162 InstrStage<1, [IWB]>], 163 [7, 4, 4], 164 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 165 InstrItinData<IntMulHW , [InstrStage<1, [IFTH1, IFTH2]>, 166 InstrStage<1, [PDCD1, PDCD2]>, 167 InstrStage<1, [DISS1, DISS2]>, 168 InstrStage<1, [IRACC]>, 169 InstrStage<1, [IEXE1]>, 170 InstrStage<1, [IEXE2]>, 171 InstrStage<1, [IWB]>], 172 [8, 4, 4], 173 [NoBypass, GPR_Bypass, GPR_Bypass]>, 174 InstrItinData<IntMulHWU , [InstrStage<1, [IFTH1, IFTH2]>, 175 InstrStage<1, [PDCD1, PDCD2]>, 176 InstrStage<1, [DISS1, DISS2]>, 177 InstrStage<1, [IRACC]>, 178 InstrStage<1, [IEXE1]>, 179 InstrStage<1, [IEXE2]>, 180 InstrStage<1, [IWB]>], 181 [8, 4, 4], 182 [NoBypass, GPR_Bypass, GPR_Bypass]>, 183 InstrItinData<IntMulLI , [InstrStage<1, [IFTH1, IFTH2]>, 184 InstrStage<1, [PDCD1, PDCD2]>, 185 InstrStage<1, [DISS1, DISS2]>, 186 InstrStage<1, [IRACC]>, 187 InstrStage<1, [IEXE1]>, 188 InstrStage<1, [IEXE2]>, 189 InstrStage<1, [IWB]>], 190 [8, 4, 4], 191 [NoBypass, GPR_Bypass, GPR_Bypass]>, 192 InstrItinData<IntRotate , [InstrStage<1, [IFTH1, IFTH2]>, 193 InstrStage<1, [PDCD1, PDCD2]>, 194 InstrStage<1, [DISS1, DISS2]>, 195 InstrStage<1, [IRACC, LRACC]>, 196 InstrStage<1, [IEXE1, JEXE1]>, 197 InstrStage<1, [IEXE2, JEXE2]>, 198 InstrStage<1, [IWB, JWB]>], 199 [6, 4, 4], 200 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 201 InstrItinData<IntShift , [InstrStage<1, [IFTH1, IFTH2]>, 202 InstrStage<1, [PDCD1, PDCD2]>, 203 InstrStage<1, [DISS1, DISS2]>, 204 InstrStage<1, [IRACC, LRACC]>, 205 InstrStage<1, [IEXE1, JEXE1]>, 206 InstrStage<1, [IEXE2, JEXE2]>, 207 InstrStage<1, [IWB, JWB]>], 208 [6, 4, 4], 209 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, 210 InstrItinData<IntTrapW , [InstrStage<1, [IFTH1, IFTH2]>, 211 InstrStage<1, [PDCD1, PDCD2]>, 212 InstrStage<1, [DISS1, DISS2]>, 213 InstrStage<1, [IRACC]>, 214 InstrStage<1, [IEXE1]>, 215 InstrStage<1, [IEXE2]>, 216 InstrStage<1, [IWB]>], 217 [6, 4], 218 [GPR_Bypass, GPR_Bypass]>, 219 InstrItinData<BrB , [InstrStage<1, [IFTH1, IFTH2]>, 220 InstrStage<1, [PDCD1, PDCD2]>, 221 InstrStage<1, [DISS1, DISS2]>, 222 InstrStage<1, [IRACC]>, 223 InstrStage<1, [IEXE1]>, 224 InstrStage<1, [IEXE2]>, 225 InstrStage<1, [IWB]>], 226 [8, 4], 227 [NoBypass, GPR_Bypass]>, 228 InstrItinData<BrCR , [InstrStage<1, [IFTH1, IFTH2]>, 229 InstrStage<1, [PDCD1, PDCD2]>, 230 InstrStage<1, [DISS1, DISS2]>, 231 InstrStage<1, [IRACC]>, 232 InstrStage<1, [IEXE1]>, 233 InstrStage<1, [IEXE2]>, 234 InstrStage<1, [IWB]>], 235 [8, 4, 4], 236 [NoBypass, GPR_Bypass, GPR_Bypass]>, 237 InstrItinData<BrMCR , [InstrStage<1, [IFTH1, IFTH2]>, 238 InstrStage<1, [PDCD1, PDCD2]>, 239 InstrStage<1, [DISS1, DISS2]>, 240 InstrStage<1, [IRACC]>, 241 InstrStage<1, [IEXE1]>, 242 InstrStage<1, [IEXE2]>, 243 InstrStage<1, [IWB]>], 244 [8, 4, 4], 245 [NoBypass, GPR_Bypass, GPR_Bypass]>, 246 InstrItinData<BrMCRX , [InstrStage<1, [IFTH1, IFTH2]>, 247 InstrStage<1, [PDCD1, PDCD2]>, 248 InstrStage<1, [DISS1, DISS2]>, 249 InstrStage<1, [IRACC]>, 250 InstrStage<1, [IEXE1]>, 251 InstrStage<1, [IEXE2]>, 252 InstrStage<1, [IWB]>], 253 [8, 4, 4], 254 [NoBypass, GPR_Bypass, GPR_Bypass]>, 255 InstrItinData<LdStDCBA , [InstrStage<1, [IFTH1, IFTH2]>, 256 InstrStage<1, [PDCD1, PDCD2]>, 257 InstrStage<1, [DISS1, DISS2]>, 258 InstrStage<1, [LRACC]>, 259 InstrStage<1, [AGEN]>, 260 InstrStage<1, [CRD]>, 261 InstrStage<1, [LWB]>], 262 [8, 5], 263 [NoBypass, GPR_Bypass]>, 264 InstrItinData<LdStDCBF , [InstrStage<1, [IFTH1, IFTH2]>, 265 InstrStage<1, [PDCD1, PDCD2]>, 266 InstrStage<1, [DISS1, DISS2]>, 267 InstrStage<1, [LRACC]>, 268 InstrStage<1, [AGEN]>, 269 InstrStage<1, [CRD]>, 270 InstrStage<1, [LWB]>], 271 [8, 5], 272 [NoBypass, GPR_Bypass]>, 273 InstrItinData<LdStDCBI , [InstrStage<1, [IFTH1, IFTH2]>, 274 InstrStage<1, [PDCD1, PDCD2]>, 275 InstrStage<1, [DISS1, DISS2]>, 276 InstrStage<1, [LRACC]>, 277 InstrStage<1, [AGEN]>, 278 InstrStage<1, [CRD]>, 279 InstrStage<1, [LWB]>], 280 [8, 5], 281 [NoBypass, GPR_Bypass]>, 282 InstrItinData<LdStLoad , [InstrStage<1, [IFTH1, IFTH2]>, 283 InstrStage<1, [PDCD1, PDCD2]>, 284 InstrStage<1, [DISS1, DISS2]>, 285 InstrStage<1, [LRACC]>, 286 InstrStage<1, [AGEN]>, 287 InstrStage<1, [CRD]>, 288 InstrStage<2, [LWB]>], 289 [9, 5], 290 [GPR_Bypass, GPR_Bypass]>, 291 InstrItinData<LdStLoadUpd , [InstrStage<1, [IFTH1, IFTH2]>, 292 InstrStage<1, [PDCD1, PDCD2]>, 293 InstrStage<1, [DISS1, DISS2]>, 294 InstrStage<1, [LRACC]>, 295 InstrStage<1, [AGEN]>, 296 InstrStage<1, [CRD]>, 297 InstrStage<2, [LWB]>], 298 [9, 5], 299 [GPR_Bypass, GPR_Bypass]>, 300 InstrItinData<LdStStore , [InstrStage<1, [IFTH1, IFTH2]>, 301 InstrStage<1, [PDCD1, PDCD2]>, 302 InstrStage<1, [DISS1, DISS2]>, 303 InstrStage<1, [LRACC]>, 304 InstrStage<1, [AGEN]>, 305 InstrStage<1, [CRD]>, 306 InstrStage<2, [LWB]>], 307 [8, 5], 308 [NoBypass, GPR_Bypass]>, 309 InstrItinData<LdStStoreUpd, [InstrStage<1, [IFTH1, IFTH2]>, 310 InstrStage<1, [PDCD1, PDCD2]>, 311 InstrStage<1, [DISS1, DISS2]>, 312 InstrStage<1, [LRACC]>, 313 InstrStage<1, [AGEN]>, 314 InstrStage<1, [CRD]>, 315 InstrStage<2, [LWB]>], 316 [8, 5], 317 [NoBypass, GPR_Bypass]>, 318 InstrItinData<LdStICBI , [InstrStage<1, [IFTH1, IFTH2]>, 319 InstrStage<1, [PDCD1, PDCD2]>, 320 InstrStage<1, [DISS1, DISS2]>, 321 InstrStage<1, [LRACC]>, 322 InstrStage<1, [AGEN]>, 323 InstrStage<1, [CRD]>, 324 InstrStage<1, [LWB]>], 325 [8, 5], 326 [NoBypass, GPR_Bypass]>, 327 InstrItinData<LdStSTFD , [InstrStage<1, [IFTH1, IFTH2]>, 328 InstrStage<1, [PDCD1, PDCD2]>, 329 InstrStage<1, [DISS1, DISS2]>, 330 InstrStage<1, [LRACC]>, 331 InstrStage<1, [AGEN]>, 332 InstrStage<1, [CRD]>, 333 InstrStage<1, [LWB]>], 334 [8, 5, 5], 335 [NoBypass, GPR_Bypass, GPR_Bypass]>, 336 InstrItinData<LdStSTFDU , [InstrStage<1, [IFTH1, IFTH2]>, 337 InstrStage<1, [PDCD1, PDCD2]>, 338 InstrStage<1, [DISS1, DISS2]>, 339 InstrStage<1, [LRACC]>, 340 InstrStage<1, [AGEN]>, 341 InstrStage<1, [CRD]>, 342 InstrStage<1, [LWB]>], 343 [8, 5, 5], 344 [NoBypass, GPR_Bypass, GPR_Bypass]>, 345 InstrItinData<LdStLFD , [InstrStage<1, [IFTH1, IFTH2]>, 346 InstrStage<1, [PDCD1, PDCD2]>, 347 InstrStage<1, [DISS1, DISS2]>, 348 InstrStage<1, [LRACC]>, 349 InstrStage<1, [AGEN]>, 350 InstrStage<1, [CRD]>, 351 InstrStage<2, [LWB]>], 352 [9, 5, 5], 353 [NoBypass, GPR_Bypass, GPR_Bypass]>, 354 InstrItinData<LdStLFDU , [InstrStage<1, [IFTH1, IFTH2]>, 355 InstrStage<1, [PDCD1, PDCD2]>, 356 InstrStage<1, [DISS1, DISS2]>, 357 InstrStage<1, [LRACC]>, 358 InstrStage<1, [AGEN]>, 359 InstrStage<1, [CRD]>, 360 InstrStage<1, [LWB]>], 361 [9, 5, 5], 362 [NoBypass, GPR_Bypass, GPR_Bypass]>, 363 InstrItinData<LdStLHA , [InstrStage<1, [IFTH1, IFTH2]>, 364 InstrStage<1, [PDCD1, PDCD2]>, 365 InstrStage<1, [DISS1, DISS2]>, 366 InstrStage<1, [LRACC]>, 367 InstrStage<1, [AGEN]>, 368 InstrStage<1, [CRD]>, 369 InstrStage<1, [LWB]>], 370 [8, 5], 371 [NoBypass, GPR_Bypass]>, 372 InstrItinData<LdStLHAU , [InstrStage<1, [IFTH1, IFTH2]>, 373 InstrStage<1, [PDCD1, PDCD2]>, 374 InstrStage<1, [DISS1, DISS2]>, 375 InstrStage<1, [LRACC]>, 376 InstrStage<1, [AGEN]>, 377 InstrStage<1, [CRD]>, 378 InstrStage<1, [LWB]>], 379 [8, 5], 380 [NoBypass, GPR_Bypass]>, 381 InstrItinData<LdStLMW , [InstrStage<1, [IFTH1, IFTH2]>, 382 InstrStage<1, [PDCD1, PDCD2]>, 383 InstrStage<1, [DISS1, DISS2]>, 384 InstrStage<1, [LRACC]>, 385 InstrStage<1, [AGEN]>, 386 InstrStage<1, [CRD]>, 387 InstrStage<1, [LWB]>], 388 [8, 5], 389 [NoBypass, GPR_Bypass]>, 390 InstrItinData<LdStLWARX , [InstrStage<1, [IFTH1, IFTH2]>, 391 InstrStage<1, [PDCD1, PDCD2]>, 392 InstrStage<1, [DISS1]>, 393 InstrStage<1, [IRACC], 0>, 394 InstrStage<4, [LWARX_Hold], 0>, 395 InstrStage<1, [LRACC]>, 396 InstrStage<1, [AGEN]>, 397 InstrStage<1, [CRD]>, 398 InstrStage<1, [LWB]>], 399 [8, 5], 400 [NoBypass, GPR_Bypass]>, 401 InstrItinData<LdStSTD , [InstrStage<1, [IFTH1, IFTH2]>, 402 InstrStage<1, [PDCD1, PDCD2]>, 403 InstrStage<1, [DISS1, DISS2]>, 404 InstrStage<1, [LRACC]>, 405 InstrStage<1, [AGEN]>, 406 InstrStage<1, [CRD]>, 407 InstrStage<2, [LWB]>], 408 [8, 5], 409 [NoBypass, GPR_Bypass]>, 410 InstrItinData<LdStSTDU , [InstrStage<1, [IFTH1, IFTH2]>, 411 InstrStage<1, [PDCD1, PDCD2]>, 412 InstrStage<1, [DISS1, DISS2]>, 413 InstrStage<1, [LRACC]>, 414 InstrStage<1, [AGEN]>, 415 InstrStage<1, [CRD]>, 416 InstrStage<2, [LWB]>], 417 [8, 5], 418 [NoBypass, GPR_Bypass]>, 419 InstrItinData<LdStSTDCX , [InstrStage<1, [IFTH1, IFTH2]>, 420 InstrStage<1, [PDCD1, PDCD2]>, 421 InstrStage<1, [DISS1]>, 422 InstrStage<1, [IRACC], 0>, 423 InstrStage<4, [LWARX_Hold], 0>, 424 InstrStage<1, [LRACC]>, 425 InstrStage<1, [AGEN]>, 426 InstrStage<1, [CRD]>, 427 InstrStage<1, [LWB]>], 428 [8, 5], 429 [NoBypass, GPR_Bypass]>, 430 InstrItinData<LdStSTWCX , [InstrStage<1, [IFTH1, IFTH2]>, 431 InstrStage<1, [PDCD1, PDCD2]>, 432 InstrStage<1, [DISS1]>, 433 InstrStage<1, [IRACC], 0>, 434 InstrStage<4, [LWARX_Hold], 0>, 435 InstrStage<1, [LRACC]>, 436 InstrStage<1, [AGEN]>, 437 InstrStage<1, [CRD]>, 438 InstrStage<1, [LWB]>], 439 [8, 5], 440 [NoBypass, GPR_Bypass]>, 441 InstrItinData<LdStSync , [InstrStage<1, [IFTH1, IFTH2]>, 442 InstrStage<1, [PDCD1, PDCD2]>, 443 InstrStage<1, [DISS1, DISS2]>, 444 InstrStage<1, [LRACC]>, 445 InstrStage<3, [AGEN], 1>, 446 InstrStage<2, [CRD], 1>, 447 InstrStage<1, [LWB]>]>, 448 InstrItinData<SprISYNC , [InstrStage<1, [IFTH1, IFTH2]>, 449 InstrStage<1, [PDCD1, PDCD2]>, 450 InstrStage<1, [DISS1, DISS2]>, 451 InstrStage<1, [FRACC], 0>, 452 InstrStage<1, [LRACC], 0>, 453 InstrStage<1, [IRACC]>, 454 InstrStage<1, [FEXE1], 0>, 455 InstrStage<1, [AGEN], 0>, 456 InstrStage<1, [JEXE1], 0>, 457 InstrStage<1, [IEXE1]>, 458 InstrStage<1, [FEXE2], 0>, 459 InstrStage<1, [CRD], 0>, 460 InstrStage<1, [JEXE2], 0>, 461 InstrStage<1, [IEXE2]>, 462 InstrStage<6, [FEXE3], 0>, 463 InstrStage<6, [LWB], 0>, 464 InstrStage<6, [JWB], 0>, 465 InstrStage<6, [IWB]>]>, 466 InstrItinData<SprMFSR , [InstrStage<1, [IFTH1, IFTH2]>, 467 InstrStage<1, [PDCD1, PDCD2]>, 468 InstrStage<1, [DISS1, DISS2]>, 469 InstrStage<1, [IRACC]>, 470 InstrStage<1, [IEXE1]>, 471 InstrStage<1, [IEXE2]>, 472 InstrStage<1, [IWB]>], 473 [6, 4], 474 [GPR_Bypass, GPR_Bypass]>, 475 InstrItinData<SprMTMSR , [InstrStage<1, [IFTH1, IFTH2]>, 476 InstrStage<1, [PDCD1, PDCD2]>, 477 InstrStage<1, [DISS1, DISS2]>, 478 InstrStage<1, [IRACC]>, 479 InstrStage<1, [IEXE1]>, 480 InstrStage<1, [IEXE2]>, 481 InstrStage<1, [IWB]>], 482 [6, 4], 483 [GPR_Bypass, GPR_Bypass]>, 484 InstrItinData<SprMTSR , [InstrStage<1, [IFTH1, IFTH2]>, 485 InstrStage<1, [PDCD1, PDCD2]>, 486 InstrStage<1, [DISS1, DISS2]>, 487 InstrStage<1, [IRACC]>, 488 InstrStage<1, [IEXE1]>, 489 InstrStage<1, [IEXE2]>, 490 InstrStage<3, [IWB]>], 491 [9, 4], 492 [NoBypass, GPR_Bypass]>, 493 InstrItinData<SprTLBSYNC , [InstrStage<1, [IFTH1, IFTH2]>, 494 InstrStage<1, [PDCD1, PDCD2]>, 495 InstrStage<1, [DISS1, DISS2]>, 496 InstrStage<1, [IRACC]>, 497 InstrStage<1, [IEXE1]>, 498 InstrStage<1, [IEXE2]>, 499 InstrStage<1, [IWB]>]>, 500 InstrItinData<SprMFCR , [InstrStage<1, [IFTH1, IFTH2]>, 501 InstrStage<1, [PDCD1, PDCD2]>, 502 InstrStage<1, [DISS1, DISS2]>, 503 InstrStage<1, [IRACC]>, 504 InstrStage<1, [IEXE1]>, 505 InstrStage<1, [IEXE2]>, 506 InstrStage<1, [IWB]>], 507 [8, 4], 508 [NoBypass, GPR_Bypass]>, 509 InstrItinData<SprMFMSR , [InstrStage<1, [IFTH1, IFTH2]>, 510 InstrStage<1, [PDCD1, PDCD2]>, 511 InstrStage<1, [DISS1, DISS2]>, 512 InstrStage<1, [IRACC]>, 513 InstrStage<1, [IEXE1]>, 514 InstrStage<1, [IEXE2]>, 515 InstrStage<1, [IWB]>], 516 [7, 4], 517 [GPR_Bypass, GPR_Bypass]>, 518 InstrItinData<SprMFSPR , [InstrStage<1, [IFTH1, IFTH2]>, 519 InstrStage<1, [PDCD1, PDCD2]>, 520 InstrStage<1, [DISS1, DISS2]>, 521 InstrStage<1, [IRACC]>, 522 InstrStage<1, [IEXE1]>, 523 InstrStage<1, [IEXE2]>, 524 InstrStage<3, [IWB]>], 525 [10, 4], 526 [NoBypass, GPR_Bypass]>, 527 InstrItinData<SprMFTB , [InstrStage<1, [IFTH1, IFTH2]>, 528 InstrStage<1, [PDCD1, PDCD2]>, 529 InstrStage<1, [DISS1, DISS2]>, 530 InstrStage<1, [IRACC]>, 531 InstrStage<1, [IEXE1]>, 532 InstrStage<1, [IEXE2]>, 533 InstrStage<3, [IWB]>], 534 [10, 4], 535 [NoBypass, GPR_Bypass]>, 536 InstrItinData<SprMTSPR , [InstrStage<1, [IFTH1, IFTH2]>, 537 InstrStage<1, [PDCD1, PDCD2]>, 538 InstrStage<1, [DISS1, DISS2]>, 539 InstrStage<1, [IRACC]>, 540 InstrStage<1, [IEXE1]>, 541 InstrStage<1, [IEXE2]>, 542 InstrStage<3, [IWB]>], 543 [10, 4], 544 [NoBypass, GPR_Bypass]>, 545 InstrItinData<SprMTSRIN , [InstrStage<1, [IFTH1, IFTH2]>, 546 InstrStage<1, [PDCD1, PDCD2]>, 547 InstrStage<1, [DISS1, DISS2]>, 548 InstrStage<1, [IRACC]>, 549 InstrStage<1, [IEXE1]>, 550 InstrStage<1, [IEXE2]>, 551 InstrStage<3, [IWB]>], 552 [10, 4], 553 [NoBypass, GPR_Bypass]>, 554 InstrItinData<SprRFI , [InstrStage<1, [IFTH1, IFTH2]>, 555 InstrStage<1, [PDCD1, PDCD2]>, 556 InstrStage<1, [DISS1, DISS2]>, 557 InstrStage<1, [IRACC]>, 558 InstrStage<1, [IEXE1]>, 559 InstrStage<1, [IEXE2]>, 560 InstrStage<1, [IWB]>], 561 [8, 4], 562 [NoBypass, GPR_Bypass]>, 563 InstrItinData<SprSC , [InstrStage<1, [IFTH1, IFTH2]>, 564 InstrStage<1, [PDCD1, PDCD2]>, 565 InstrStage<1, [DISS1, DISS2]>, 566 InstrStage<1, [IRACC]>, 567 InstrStage<1, [IEXE1]>, 568 InstrStage<1, [IEXE2]>, 569 InstrStage<1, [IWB]>], 570 [8, 4], 571 [NoBypass, GPR_Bypass]>, 572 InstrItinData<FPGeneral , [InstrStage<1, [IFTH1, IFTH2]>, 573 InstrStage<1, [PDCD1, PDCD2]>, 574 InstrStage<1, [DISS1, DISS2]>, 575 InstrStage<1, [FRACC]>, 576 InstrStage<1, [FEXE1]>, 577 InstrStage<1, [FEXE2]>, 578 InstrStage<1, [FEXE3]>, 579 InstrStage<1, [FEXE4]>, 580 InstrStage<1, [FEXE5]>, 581 InstrStage<1, [FEXE6]>, 582 InstrStage<1, [FWB]>], 583 [10, 4, 4], 584 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, 585 InstrItinData<FPAddSub , [InstrStage<1, [IFTH1, IFTH2]>, 586 InstrStage<1, [PDCD1, PDCD2]>, 587 InstrStage<1, [DISS1, DISS2]>, 588 InstrStage<1, [FRACC]>, 589 InstrStage<1, [FEXE1]>, 590 InstrStage<1, [FEXE2]>, 591 InstrStage<1, [FEXE3]>, 592 InstrStage<1, [FEXE4]>, 593 InstrStage<1, [FEXE5]>, 594 InstrStage<1, [FEXE6]>, 595 InstrStage<1, [FWB]>], 596 [10, 4, 4], 597 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, 598 InstrItinData<FPCompare , [InstrStage<1, [IFTH1, IFTH2]>, 599 InstrStage<1, [PDCD1, PDCD2]>, 600 InstrStage<1, [DISS1, DISS2]>, 601 InstrStage<1, [FRACC]>, 602 InstrStage<1, [FEXE1]>, 603 InstrStage<1, [FEXE2]>, 604 InstrStage<1, [FEXE3]>, 605 InstrStage<1, [FEXE4]>, 606 InstrStage<1, [FEXE5]>, 607 InstrStage<1, [FEXE6]>, 608 InstrStage<1, [FWB]>], 609 [10, 4, 4], 610 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, 611 InstrItinData<FPDivD , [InstrStage<1, [IFTH1, IFTH2]>, 612 InstrStage<1, [PDCD1, PDCD2]>, 613 InstrStage<1, [DISS1, DISS2]>, 614 InstrStage<1, [FRACC]>, 615 InstrStage<1, [FEXE1]>, 616 InstrStage<1, [FEXE2]>, 617 InstrStage<1, [FEXE3]>, 618 InstrStage<1, [FEXE4]>, 619 InstrStage<1, [FEXE5]>, 620 InstrStage<1, [FEXE6]>, 621 InstrStage<25, [FWB]>], 622 [35, 4, 4], 623 [NoBypass, FPR_Bypass, FPR_Bypass]>, 624 InstrItinData<FPDivS , [InstrStage<1, [IFTH1, IFTH2]>, 625 InstrStage<1, [PDCD1, PDCD2]>, 626 InstrStage<1, [DISS1, DISS2]>, 627 InstrStage<1, [FRACC]>, 628 InstrStage<1, [FEXE1]>, 629 InstrStage<1, [FEXE2]>, 630 InstrStage<1, [FEXE3]>, 631 InstrStage<1, [FEXE4]>, 632 InstrStage<1, [FEXE5]>, 633 InstrStage<1, [FEXE6]>, 634 InstrStage<13, [FWB]>], 635 [23, 4, 4], 636 [NoBypass, FPR_Bypass, FPR_Bypass]>, 637 InstrItinData<FPFused , [InstrStage<1, [IFTH1, IFTH2]>, 638 InstrStage<1, [PDCD1, PDCD2]>, 639 InstrStage<1, [DISS1, DISS2]>, 640 InstrStage<1, [FRACC]>, 641 InstrStage<1, [FEXE1]>, 642 InstrStage<1, [FEXE2]>, 643 InstrStage<1, [FEXE3]>, 644 InstrStage<1, [FEXE4]>, 645 InstrStage<1, [FEXE5]>, 646 InstrStage<1, [FEXE6]>, 647 InstrStage<1, [FWB]>], 648 [10, 4, 4, 4], 649 [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>, 650 InstrItinData<FPRes , [InstrStage<1, [IFTH1, IFTH2]>, 651 InstrStage<1, [PDCD1, PDCD2]>, 652 InstrStage<1, [DISS1, DISS2]>, 653 InstrStage<1, [FRACC]>, 654 InstrStage<1, [FEXE1]>, 655 InstrStage<1, [FEXE2]>, 656 InstrStage<1, [FEXE3]>, 657 InstrStage<1, [FEXE4]>, 658 InstrStage<1, [FEXE5]>, 659 InstrStage<1, [FEXE6]>, 660 InstrStage<1, [FWB]>], 661 [10, 4], 662 [FPR_Bypass, FPR_Bypass]> 663 ]>; 664
