1 /* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef _VM_ENC_WRAPPER_H_ 18 #define _VM_ENC_WRAPPER_H_ 19 20 #include "enc_defs_ext.h" 21 22 extern bool dump_x86_inst; 23 typedef enum PhysicalReg { 24 PhysicalReg_EAX = 0, PhysicalReg_EBX, PhysicalReg_ECX, PhysicalReg_EDX, 25 PhysicalReg_EDI, PhysicalReg_ESI, PhysicalReg_ESP, PhysicalReg_EBP, 26 PhysicalReg_XMM0, PhysicalReg_XMM1, PhysicalReg_XMM2, PhysicalReg_XMM3, 27 PhysicalReg_XMM4, PhysicalReg_XMM5, PhysicalReg_XMM6, PhysicalReg_XMM7, 28 PhysicalReg_ST0, PhysicalReg_ST1, PhysicalReg_ST2, PhysicalReg_ST3, 29 PhysicalReg_ST4, PhysicalReg_ST5, PhysicalReg_ST6, PhysicalReg_ST7, 30 PhysicalReg_Null, 31 //used as scratch logical register in NCG O1 32 //should not overlap with regular logical register, start from 100 33 PhysicalReg_SCRATCH_1 = 100, PhysicalReg_SCRATCH_2, PhysicalReg_SCRATCH_3, PhysicalReg_SCRATCH_4, 34 PhysicalReg_SCRATCH_5, PhysicalReg_SCRATCH_6, PhysicalReg_SCRATCH_7, PhysicalReg_SCRATCH_8, 35 PhysicalReg_SCRATCH_9, PhysicalReg_SCRATCH_10, 36 PhysicalReg_GLUE_DVMDEX = 900, 37 PhysicalReg_GLUE = 901 38 } PhysicalReg; 39 40 typedef enum Reg_No { 41 #ifdef _EM64T_ 42 rax_reg = 0,rbx_reg, rcx_reg, rdx_reg, 43 rdi_reg, rsi_reg, rsp_reg, rbp_reg, 44 r8_reg, r9_reg, r10_reg, r11_reg, 45 r12_reg, r13_reg, r14_reg, r15_reg, 46 xmm0_reg, xmm1_reg, xmm2_reg, xmm3_reg, 47 xmm4_reg, xmm5_reg, xmm6_reg, xmm7_reg, 48 xmm8_reg, xmm9_reg, xmm10_reg, xmm11_reg, 49 xmm12_reg, xmm13_reg, xmm14_reg, xmm15_reg, 50 51 #else // !defined(_EM64T_) 52 53 eax_reg = 0,ebx_reg, ecx_reg, edx_reg, 54 edi_reg, esi_reg, esp_reg, ebp_reg, 55 xmm0_reg, xmm1_reg, xmm2_reg, xmm3_reg, 56 xmm4_reg, xmm5_reg, xmm6_reg, xmm7_reg, 57 fs_reg, 58 #endif 59 /** @brief Total number of registers.*/ 60 n_reg 61 } Reg_No; 62 // 63 // instruction operand sizes: 8,16,32,64 bits 64 // 65 typedef enum Opnd_Size { 66 size_8 = 0, 67 size_16, 68 size_32, 69 size_64, 70 n_size, 71 #ifdef _EM64T_ 72 size_platf = size_64 73 #else 74 size_platf = size_32 75 #endif 76 } Opnd_Size; 77 78 // 79 // opcodes for alu instructions 80 // 81 typedef enum ALU_Opcode { 82 add_opc = 0,or_opc, adc_opc, sbb_opc, 83 and_opc, sub_opc, xor_opc, cmp_opc, 84 mul_opc, imul_opc, div_opc, idiv_opc, 85 sll_opc, srl_opc, sra_opc, //shift right arithmetic 86 shl_opc, shr_opc, 87 sal_opc, sar_opc, 88 neg_opc, not_opc, andn_opc, 89 n_alu 90 } ALU_Opcode; 91 92 typedef enum ConditionCode { 93 Condition_O = 0, 94 Condition_NO = 1, 95 Condition_B = 2, 96 Condition_NAE = Condition_B, 97 Condition_C = Condition_B, 98 Condition_NB = 3, 99 Condition_AE = Condition_NB, 100 Condition_NC = Condition_NB, 101 Condition_Z = 4, 102 Condition_E = Condition_Z, 103 Condition_NZ = 5, 104 Condition_NE = Condition_NZ, 105 Condition_BE = 6, 106 Condition_NA = Condition_BE, 107 Condition_NBE = 7, 108 Condition_A = Condition_NBE, 109 110 Condition_S = 8, 111 Condition_NS = 9, 112 Condition_P = 10, 113 Condition_PE = Condition_P, 114 Condition_NP = 11, 115 Condition_PO = Condition_NP, 116 Condition_L = 12, 117 Condition_NGE = Condition_L, 118 Condition_NL = 13, 119 Condition_GE = Condition_NL, 120 Condition_LE = 14, 121 Condition_NG = Condition_LE, 122 Condition_NLE = 15, 123 Condition_G = Condition_NLE, 124 Condition_Count = 16 125 } ConditionCode; 126 127 // 128 // prefix code 129 // 130 typedef enum InstrPrefix { 131 no_prefix, 132 lock_prefix = 0xF0, 133 hint_branch_taken_prefix = 0x2E, 134 hint_branch_not_taken_prefix = 0x3E, 135 prefix_repne = 0xF2, 136 prefix_repnz = prefix_repne, 137 prefix_repe = 0xF3, 138 prefix_repz = prefix_repe, 139 prefix_rep = 0xF3, 140 prefix_cs = 0x2E, 141 prefix_ss = 0x36, 142 prefix_ds = 0x3E, 143 prefix_es = 0x26, 144 prefix_fs = 0x64, 145 prefix_gs = 0x65 146 } InstrPrefix; 147 148 //last 2 bits: decide xmm, gp, fs 149 //virtual, scratch, temp, hard match with ncg_o1_data.h 150 typedef enum LowOpndRegType { 151 LowOpndRegType_gp = 0, 152 LowOpndRegType_fs = 1, 153 LowOpndRegType_xmm = 2, 154 LowOpndRegType_fs_s = 3, 155 LowOpndRegType_ss = 4, 156 LowOpndRegType_scratch = 8, //used by NCG O1 157 LowOpndRegType_temp = 16, 158 LowOpndRegType_hard = 32, //NCG O1 159 LowOpndRegType_virtual = 64, //used by NCG O1 160 LowOpndRegType_glue = 128 161 } LowOpndRegType; 162 163 //if inline, separte enc_wrapper.cpp into two files, one of them is .inl 164 // enc_wrapper.cpp needs to handle both cases 165 #ifdef ENCODER_INLINE 166 #define ENCODER_DECLARE_EXPORT inline 167 #include "enc_wrapper.inl" 168 #else 169 #define ENCODER_DECLARE_EXPORT 170 #endif 171 172 #ifdef __cplusplus 173 extern "C" 174 { 175 #endif 176 ENCODER_DECLARE_EXPORT char* encoder_imm(Mnemonic m, OpndSize size, 177 int imm, char* stream); 178 ENCODER_DECLARE_EXPORT unsigned encoder_get_inst_size(char * stream); 179 ENCODER_DECLARE_EXPORT char* encoder_update_imm(int imm, char * stream); 180 ENCODER_DECLARE_EXPORT char* encoder_mem(Mnemonic m, OpndSize size, 181 int disp, int base_reg, bool isBasePhysical, char* stream); 182 ENCODER_DECLARE_EXPORT char* encoder_reg(Mnemonic m, OpndSize size, 183 int reg, bool isPhysical, LowOpndRegType type, char* stream); 184 ENCODER_DECLARE_EXPORT char* encoder_reg_reg(Mnemonic m, OpndSize size, 185 int reg, bool isPhysical, 186 int reg2, bool isPhysical2, LowOpndRegType type, char* stream); 187 ENCODER_DECLARE_EXPORT char* encoder_mem_reg(Mnemonic m, OpndSize size, 188 int disp, int base_reg, bool isBasePhysical, 189 int reg, bool isPhysical, LowOpndRegType type, char* stream); 190 ENCODER_DECLARE_EXPORT char* encoder_mem_scale_reg(Mnemonic m, OpndSize size, 191 int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, 192 int reg, bool isPhysical, LowOpndRegType type, char* stream); 193 ENCODER_DECLARE_EXPORT char* encoder_reg_mem_scale(Mnemonic m, OpndSize size, 194 int reg, bool isPhysical, 195 int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, 196 LowOpndRegType type, char* stream); 197 ENCODER_DECLARE_EXPORT char * encoder_mem_disp_scale_reg(Mnemonic m, OpndSize size, 198 int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, 199 int reg, bool isPhysical, LowOpndRegType type, char * stream); 200 ENCODER_DECLARE_EXPORT char * encoder_movzs_mem_disp_scale_reg(Mnemonic m, OpndSize size, 201 int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, 202 int reg, bool isPhysical, LowOpndRegType type, char * stream); 203 ENCODER_DECLARE_EXPORT char* encoder_reg_mem_disp_scale(Mnemonic m, OpndSize size, 204 int reg, bool isPhysical, 205 int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, 206 LowOpndRegType type, char* stream); 207 ENCODER_DECLARE_EXPORT char* encoder_reg_mem(Mnemonic m, OpndSize size, 208 int reg, bool isPhysical, 209 int disp, int base_reg, bool isBasePhysical, LowOpndRegType type, char* stream); 210 ENCODER_DECLARE_EXPORT char* encoder_imm_reg(Mnemonic m, OpndSize size, 211 int imm, int reg, bool isPhysical, LowOpndRegType type, char* stream); 212 ENCODER_DECLARE_EXPORT char * encoder_update_imm_rm(int imm, char * stream); 213 ENCODER_DECLARE_EXPORT char* encoder_imm_mem(Mnemonic m, OpndSize size, 214 int imm, 215 int disp, int base_reg, bool isBasePhysical, char* stream); 216 ENCODER_DECLARE_EXPORT char* encoder_fp_mem(Mnemonic m, OpndSize size, int reg, 217 int disp, int base_reg, bool isBasePhysical, char* stream); 218 ENCODER_DECLARE_EXPORT char* encoder_mem_fp(Mnemonic m, OpndSize size, 219 int disp, int base_reg, bool isBasePhysical, 220 int reg, char* stream); 221 ENCODER_DECLARE_EXPORT char* encoder_return(char* stream); 222 ENCODER_DECLARE_EXPORT char* encoder_compare_fp_stack(bool pop, int reg, bool isDouble, char* stream); 223 ENCODER_DECLARE_EXPORT char* encoder_movez_mem_to_reg(OpndSize size, 224 int disp, int base_reg, bool isBasePhysical, 225 int reg, bool isPhysical, char* stream); 226 ENCODER_DECLARE_EXPORT char* encoder_moves_mem_to_reg(OpndSize size, 227 int disp, int base_reg, bool isBasePhysical, 228 int reg, bool isPhysical, char* stream); 229 ENCODER_DECLARE_EXPORT char * encoder_movez_reg_to_reg(OpndSize size, 230 int reg, bool isPhysical, int reg2, 231 bool isPhysical2, LowOpndRegType type, char * stream); 232 ENCODER_DECLARE_EXPORT char * encoder_moves_reg_to_reg(OpndSize size, 233 int reg, bool isPhysical, int reg2, 234 bool isPhysical2, LowOpndRegType type, char * stream); 235 ENCODER_DECLARE_EXPORT int decodeThenPrint(char* stream_start); 236 ENCODER_DECLARE_EXPORT char* decoder_disassemble_instr(char* stream, char* strbuf, unsigned int len); 237 #ifdef __cplusplus 238 } 239 #endif 240 #endif // _VM_ENC_WRAPPER_H_ 241
