| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 88 BuildMI (*MBB, MII, MI->getDebugLoc(),
90 BuildMI (*MBB, MII, MI->getDebugLoc(),
101 BuildMI (*MBB, MII, MI->getDebugLoc(),
103 BuildMI (*MBB, MII, MI->getDebugLoc(),
114 BuildMI (*MBB, MII, MI->getDebugLoc(),
116 BuildMI (*MBB, MII, MI->getDebugLoc(),
127 BuildMI (*MBB, MII, MI->getDebugLoc(),
129 BuildMI (*MBB, MII, MI->getDebugLoc(),
146 BuildMI (*MBB, MII, MI->getDebugLoc(),
149 BuildMI (*MBB, MII, MI->getDebugLoc()
[all...] |
| HexagonExpandPredSpillCode.cpp | 98 BuildMI(*MBB, MII, MI->getDebugLoc(),
101 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
106 BuildMI(*MBB, MII, MI->getDebugLoc(),
111 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
113 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
115 BuildMI(*MBB, MII, MI->getDebugLoc(),
122 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
124 BuildMI(*MBB, MII, MI->getDebugLoc(),
142 BuildMI(*MBB, MII, MI->getDebugLoc()
[all...] |
| HexagonSplitTFRCondSets.cpp | 114 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1),
118 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2),
133 BuildMI(*MBB, MII, MI->getDebugLoc(),
138 BuildMI(*MBB, MII, MI->getDebugLoc(),
143 BuildMI(*MBB, MII, MI->getDebugLoc(),
159 BuildMI(*MBB, MII, MI->getDebugLoc(),
164 BuildMI(*MBB, MII, MI->getDebugLoc(),
173 BuildMI(*MBB, MII, MI->getDebugLoc(),
189 BuildMI(*MBB, MII, MI->getDebugLoc(),
192 BuildMI(*MBB, MII, MI->getDebugLoc()
[all...] |
| HexagonRegisterInfo.cpp | 177 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
179 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
183 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
206 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
208 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
212 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
238 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
240 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
247 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
257 BuildMI(*MI.getParent(), II, MI.getDebugLoc()
[all...] |
| HexagonFixupHwLoops.cpp | 169 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
173 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFRI), Scratch)
175 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
179 BuildMI(*MBB, MII, DL, TII->get(Hexagon::CONST32_Label), Scratch)
181 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::SA0)
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXFrameLowering.cpp | 46 MachineInstr *MI = BuildMI(
49 BuildMI(MBB, MI, dl, tm.getInstrInfo()->get(NVPTX::MOV_DEPOT_ADDR_64),
53 MachineInstr *MI = BuildMI(
56 BuildMI(MBB, MI, dl, tm.getInstrInfo()->get(NVPTX::MOV_DEPOT_ADDR),
|
| NVPTXInstrInfo.cpp | 43 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg)
46 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg)
49 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg)
52 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg)
55 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg)
58 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg)
259 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
261 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
267 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
268 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 141 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
150 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
159 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
163 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
167 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
415 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
419 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), PPC::X12);
425 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)
[all...] |
| PPCBranchSelector.cpp | 167 BuildMI(MBB, I, dl, TII->get(PPC::BCC))
170 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
172 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
174 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
176 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
182 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
|
| PPCFastISel.cpp | 136 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocCPT),
143 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDIStocHA),
145 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
165 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
171 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
174 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
179 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
219 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::RLDICR),
227 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ORIS8),
234 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ORI8)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 10 // This file exposes a function named BuildMI, which is useful for dramatically
13 // M = BuildMI(X86::ADDrr8, 2).addReg(argVal1).addReg(argVal2);
220 /// BuildMI - Builder interface. Specify how to create the initial instruction
223 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
229 /// BuildMI - This version of the builder sets up the first operand as a
232 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
240 /// BuildMI - This version of the builder inserts the newly-built
244 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
255 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
266 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB
[all...] |
| /external/llvm/lib/Target/R600/ |
| SILowerControlFlow.cpp | 138 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
155 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
160 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
172 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
181 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
184 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
199 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
203 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
219 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
234 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 197 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
199 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
232 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
240 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
242 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
246 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
277 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
280 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
284 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
296 MovMI = BuildMI(MBB, I, DL, get(SP::FMOVS), Dst).addReg(Src)
[all...] |
| SparcFrameLowering.cpp | 60 BuildMI(MBB, MBBI, dl, TII.get(SAVEri), SP::O6)
66 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
68 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
70 BuildMI(MBB, MBBI, dl, TII.get(SAVErr), SP::O6)
87 BuildMI(MBB, I, DL, TII.get(SP::ADDri), SP::O6).addReg(SP::O6)
104 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
117 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6)
123 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
125 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
127 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDrr), SP::O6
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsLongBranch.cpp | 225 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
288 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
290 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
294 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
295 .append(BuildMI(*MF, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi));
299 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::AT)
301 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
303 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
307 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
308 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP
[all...] |
| Mips16InstrInfo.cpp | 91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
112 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
129 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
180 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
185 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
199 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
203 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
207 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
222 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
231 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 172 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
177 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
183 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
193 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
198 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
204 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
222 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
227 BuildMI(MBB, II, dl, TII.get(NewOpcode))
233 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
254 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value)
[all...] |
| XCoreFrameLowering.cpp | 55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
70 BuildMI(MBB, I, dl, TII.get(Opcode))
130 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
136 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
146 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel);
158 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label);
162 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
167 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
185 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
226 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize)
[all...] |
| XCoreInstrInfo.cpp | 287 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
302 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
342 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
354 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
370 BuildMI(MBB, I, DL, get(XCore::STWFI))
384 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
156 BuildMI(MBB, MBBI, DL,
160 BuildMI(MBB, MBBI, DL,
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
199 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r))
220 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
247 New = BuildMI(MF, Old->getDebugLoc()
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
711 BuildMI(MBB, MBBI, DL,
755 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
762 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
777 BuildMI(MBB, MBBI, DL,
785 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
816 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
837 BuildMI(MBB, MBBI, DL
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 65 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
76 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
88 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
101 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::COPY))
129 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV_IMM_I32),
134 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::LSHR_eg), NewAddr)
138 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
160 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), t0)
164 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), t1)
168 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 65 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
76 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
88 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
101 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::COPY))
129 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV_IMM_I32),
134 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::LSHR_eg), NewAddr)
138 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
160 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), t0)
164 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), t1)
168 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
73 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 49 BuildMI(MBB, I, DL, get(AArch64::ADDxxi_lsl0_s), DestReg)
55 BuildMI(MBB, I, DL, get(AArch64::ADDwwi_lsl0_s), DestReg)
62 BuildMI(MBB, I, DL, get(AArch64::MSRix))
68 BuildMI(MBB, I, DL, get(AArch64::MRSxi), DestReg)
80 BuildMI(MBB, I, DL, get(AArch64::FMOVss), DestReg)
85 BuildMI(MBB, I, DL, get(AArch64::FMOVdd), DestReg)
98 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PreInd_STR), AArch64::XSP)
103 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PostInd_LDR), DestReg)
113 BuildMI(MBB, I, DL, get(Opc), DestReg)
298 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(TBB)
[all...] |
