| /external/llvm/include/llvm/CodeGen/ |
| Analysis.h | 72 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
76 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
81 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
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| ISDOpcodes.h | 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
696 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
709 enum CondCode {
[all...] |
| SelectionDAG.h | 480 SDValue getCondCode(ISD::CondCode Cond);
605 /// have an ISD::CondCode instead of an SDValue.
608 ISD::CondCode Cond) {
631 /// just have an ISD::CondCode instead of an SDValue.
634 SDValue True, SDValue False, ISD::CondCode Cond) {
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 32 enum CondCode {
130 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
143 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
154 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
214 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
236 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
299 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
395 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()))
[all...] |
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.h | 33 enum CondCode {
73 const char *MipsFCCToString(Mips::CondCode CC);
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| MipsInstPrinter.cpp | 35 const char* Mips::MipsFCCToString(Mips::CondCode CC) {
211 O << MipsFCCToString((Mips::CondCode)MO.getImm());
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_inlines.h | 26 static inline CondCode reverseCondCode(CondCode cc)
30 return static_cast<CondCode>(ccRev[cc & 7] | (cc & ~7));
33 static inline CondCode inverseCondCode(CondCode cc)
35 return static_cast<CondCode>(cc ^ 7);
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| nv50_ir.h | 168 enum CondCode
587 bool compare(CondCode cc, float fval) const;
629 bool setPredicate(CondCode ccode, Value *);
679 CondCode cc;
826 void setCondition(CondCode cond) { setCond = cond; }
827 CondCode getCondition() const { return setCond; }
830 CondCode setCond;
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| nv50_ir_build_util.h | 73 CmpInstruction *mkCmp(operation, CondCode, DataType,
80 FlowInstruction *mkFlow(operation, void *target, CondCode, Value *pred);
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| nv50_ir_build_util.cpp | 223 BuildUtil::mkCmp(operation op, CondCode cc, DataType ty, Value *dst,
307 BuildUtil::mkFlow(operation op, void *targ, CondCode cc, Value *pred)
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| nv50_ir.cpp | 459 ImmediateValue::compare(CondCode cc, float fval) const
464 switch (static_cast<CondCode>(cc & 7)) {
816 Instruction::setPredicate(CondCode ccode, Value *value)
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_inlines.h | 26 static inline CondCode reverseCondCode(CondCode cc)
30 return static_cast<CondCode>(ccRev[cc & 7] | (cc & ~7));
33 static inline CondCode inverseCondCode(CondCode cc)
35 return static_cast<CondCode>(cc ^ 7);
|
| nv50_ir.h | 168 enum CondCode
587 bool compare(CondCode cc, float fval) const;
629 bool setPredicate(CondCode ccode, Value *);
679 CondCode cc;
826 void setCondition(CondCode cond) { setCond = cond; }
827 CondCode getCondition() const { return setCond; }
830 CondCode setCond;
|
| nv50_ir_build_util.h | 73 CmpInstruction *mkCmp(operation, CondCode, DataType,
80 FlowInstruction *mkFlow(operation, void *target, CondCode, Value *pred);
|
| nv50_ir_build_util.cpp | 223 BuildUtil::mkCmp(operation op, CondCode cc, DataType ty, Value *dst,
307 BuildUtil::mkFlow(operation op, void *targ, CondCode cc, Value *pred)
|
| nv50_ir.cpp | 459 ImmediateValue::compare(CondCode cc, float fval) const
464 switch (static_cast<CondCode>(cc & 7)) {
816 Instruction::setPredicate(CondCode ccode, Value *value)
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 32 enum CondCode {
62 unsigned GetCondBranchFromCond(CondCode CC);
65 CondCode getCondFromCMovOpc(unsigned Opc);
69 CondCode GetOppositeBranchCondition(X86::CondCode CC);
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| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 628 unsigned CondCode = MI->getOperand(3).getImm();
654 .addImm(CondCode)
[all...] |
| AArch64ISelLowering.h | 75 /// compare after we've moved the CondCode information onto the SELECT_CC or
206 SDValue getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
|
| /external/llvm/lib/CodeGen/ |
| Analysis.cpp | 150 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) {
172 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) {
187 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) {
|
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 519 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
533 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 113 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
472 ISD::CondCode CC, SDLoc dl) {
569 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
600 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
632 static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC) {
714 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 197 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
207 ISD::CondCode CC;
|
| LegalizeFloatTypes.cpp | 653 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
699 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
[all...] |
