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    Searched refs:GPR2AlignEncode (Results 1 - 6 of 6) sorted by null

  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
AMDGPUCodeEmitter.h 28 virtual unsigned GPR2AlignEncode(const MachineInstr &MI,
  /external/mesa3d/src/gallium/drivers/radeon/
AMDGPUCodeEmitter.h 28 virtual unsigned GPR2AlignEncode(const MachineInstr &MI,
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
AMDGPUMCCodeEmitter.h 40 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
SIMCCodeEmitter.cpp 86 /// GPR2AlignEncode - Encoding for when 2 consecutive registers are used
87 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
167 unsigned SIMCCodeEmitter::GPR2AlignEncode(const MCInst &MI,
209 | ((GPR2AlignEncode(MI, OpNo, Fixup) & SMRD_SBASE_MASK) << SMRD_SBASE_SHIFT)
  /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
AMDGPUMCCodeEmitter.h 40 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
SIMCCodeEmitter.cpp 86 /// GPR2AlignEncode - Encoding for when 2 consecutive registers are used
87 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
167 unsigned SIMCCodeEmitter::GPR2AlignEncode(const MCInst &MI,
209 | ((GPR2AlignEncode(MI, OpNo, Fixup) & SMRD_SBASE_MASK) << SMRD_SBASE_SHIFT)

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