HomeSort by relevance Sort by last modified time
    Searched refs:RegUnit (Results 1 - 8 of 8) sorted by null

  /external/llvm/include/llvm/CodeGen/
LiveRegMatrix.h 19 // the virtual register is inserted into the LiveIntervalUnion for each regunit
130 /// Check for regunit interference only.
139 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned RegUnit);
141 /// Directly access the live interval unions per regunit.
142 /// This returns an array indexed by the regunit number.
MachineRegisterInfo.h 394 void setRegUnitUsed(unsigned RegUnit) {
395 UsedRegUnits.set(RegUnit);
  /external/llvm/lib/CodeGen/
LiveRegMatrix.cpp 129 unsigned RegUnit) {
130 LiveIntervalUnion::Query &Q = Queries[RegUnit];
131 Q.init(UserTag, &VirtReg, &Matrix[RegUnit]);
MachineTraceMetrics.cpp 681 // Associate each regunit with an instruction operand. Depending on the
683 // regunit, or the highest operand to read the regunit.
686 unsigned RegUnit;
691 unsigned getSparseSetIndex() const { return RegUnit; }
693 LiveRegUnit(unsigned RU) : RegUnit(RU), Cycle(0), MI(0), Op(0) {}
697 // Identify physreg dependencies for UseMI, and update the live regunit
    [all...]
  /external/llvm/include/llvm/MC/
MCRegisterInfo.h 162 const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table.
185 /// differentially encoded register and regunit lists in DiffLists.
528 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
529 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
530 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
531 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 410 /// hasRegUnit - Returns true if Reg contains RegUnit.
411 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
413 if (*Units == RegUnit)
615 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
634 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
    [all...]
  /external/llvm/utils/TableGen/
CodeGenRegisters.h 407 struct RegUnit {
408 // Weight assigned to this RegUnit for estimating register pressure.
413 // Each native RegUnit corresponds to one or two root registers. The full
422 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) { Roots[0] = Roots[1] = 0; }
470 SmallVector<RegUnit, 8> RegUnits;
484 // class's units and any inferred RegUnit supersets.
606 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
607 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
RegisterInfoEmitter.cpp 196 << "getRegUnitWeight(unsigned RegUnit) const {\n"
197 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
203 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
204 assert(RU.Weight < 256 && "RegUnit too heavy");
208 << " return RUWeightTable[RegUnit];\n";
299 << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
300 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
308 << " unsigned SetListStart = RUSetStartTable[RegUnit];\n"
558 // Differentially encoded register and regunit lists allow for better
832 // Emit the table of register unit roots. Each regunit has one or two roo
    [all...]

Completed in 113 milliseconds