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    Searched refs:ResultReg (Results 1 - 4 of 4) sorted by null

  /external/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp 387 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
390 if (ResultReg == 0) return false;
393 UpdateValueMap(I, ResultReg);
423 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
425 if (ResultReg == 0) return false;
428 UpdateValueMap(I, ResultReg);
434 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
436 if (ResultReg != 0) {
438 UpdateValueMap(I, ResultReg);
451 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT()
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 161 unsigned ResultReg = createResultReg(RC);
166 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
175 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
180 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
183 return ResultReg;
233 unsigned ResultReg = createResultReg(RC);
235 ResultReg).addReg(TmpReg3).addImm(Lo);
236 return ResultReg;
  /external/llvm/lib/Target/ARM/
ARMFastISel.cpp 183 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
296 unsigned ResultReg = createResultReg(RC);
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
300 return ResultReg;
306 unsigned ResultReg = createResultReg(RC);
310 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
316 TII.get(TargetOpcode::COPY), ResultReg)
319 return ResultReg;
326 unsigned ResultReg = createResultReg(RC);
330 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
    [all...]
  /external/llvm/lib/Target/X86/
X86FastISel.cpp 88 unsigned &ResultReg);
180 unsigned &ResultReg) {
227 ResultReg = createResultReg(RC);
229 DL, TII.get(Opc), ResultReg), AM);
337 unsigned &ResultReg) {
343 ResultReg = RR;
863 unsigned ResultReg = 0;
864 if (X86FastEmitLoad(VT, AM, ResultReg)) {
865 UpdateValueMap(I, ResultReg);
948 unsigned ResultReg = createResultReg(&X86::GR8RegClass)
    [all...]

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