| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 45 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
46 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
251 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
342 ISD::SELECT_CC,
403 // We need all the operands of SELECT_CC to have the same value type, so if
406 // SELECT_CC node.
420 assert(!"Unhandled operand type parings in SELECT_CC");
431 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
466 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
472 // this SELECT_CC, so we must lower it
[all...] |
| SIISelLowering.cpp | 56 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
57 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
59 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
60 setTargetDAGCombine(ISD::SELECT_CC);
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
400 case ISD::SELECT_CC: {
|
| AMDILISelLowering.cpp | 170 setOperationAction(ISD::SELECT_CC, VT, Expand);
289 case ISD::SELECT_CC:
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 45 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
46 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
251 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
342 ISD::SELECT_CC,
403 // We need all the operands of SELECT_CC to have the same value type, so if
406 // SELECT_CC node.
420 assert(!"Unhandled operand type parings in SELECT_CC");
431 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
466 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
472 // this SELECT_CC, so we must lower it
[all...] |
| SIISelLowering.cpp | 56 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
57 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
59 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
60 setTargetDAGCombine(ISD::SELECT_CC);
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
400 case ISD::SELECT_CC: {
|
| AMDILISelLowering.cpp | 170 setOperationAction(ISD::SELECT_CC, VT, Expand);
289 case ISD::SELECT_CC:
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 331 SELECT_CC,
488 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 60 /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
62 SELECT_CC,
|
| MSP430ISelLowering.cpp | 116 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
117 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
198 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 65 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
66 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
95 setTargetDAGCombine(ISD::SELECT_CC);
488 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
839 // select_cc f32, f32, -1, 0, cc_any
840 // select_cc f32, f32, 1.0f, 0.0f, cc_any
841 // select_cc i32, i32, -1, 0, cc_any
854 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
861 // select_cc f32, 0.0, f32, f32, cc_any
862 // select_cc f32, 0.0, i32, i32, cc_an
[all...] |
| SIISelLowering.cpp | 73 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
74 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
76 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
90 setTargetDAGCombine(ISD::SELECT_CC);
348 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
557 case ISD::SELECT_CC: {
[all...] |
| AMDILISelLowering.cpp | 155 setOperationAction(ISD::SELECT_CC, VT, Expand);
263 case ISD::SELECT_CC:
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 68 /// This is an A64-ification of the standard LLVM SELECT_CC operation. The
71 SELECT_CC,
75 /// compare after we've moved the CondCode information onto the SELECT_CC or
|
| AArch64ISelLowering.cpp | 107 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
108 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
109 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
110 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
235 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
814 case AArch64ISD::SELECT_CC: return "AArch64ISD::SELECT_CC";
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 513 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0),
515 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0),
|
| LegalizeFloatTypes.cpp | 97 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break;
536 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
615 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break;
[all...] |
| SelectionDAGDumper.cpp | 187 case ISD::SELECT_CC: return "select_cc";
|
| LegalizeVectorTypes.cpp | 63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
292 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
499 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
[all...] |
| LegalizeVectorOps.cpp | 220 case ISD::SELECT_CC:
|
| LegalizeIntegerTypes.cpp | 69 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
505 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
[all...] |
| DAGCombiner.cpp | 549 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
562 if (N.getOpcode() == ISD::SELECT_CC &&
[all...] |
| LegalizeDAG.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
97 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
179 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
[all...] |
